Show oper_r and oper_i in the signal list, in simulation

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index 6b0660314eb31585800ff915a57428db7a78bc5e..0267d4f9df2227d4760ce4a20d4e215dda04413a 100644 (file)
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -76,7 +76,7 @@ class CompUnitRecord(RegSpec, RecordObject):
         self._dest = dst
 
         # operation / data input
-        self.oper_i = subkls() # operand
+        self.oper_i = subkls(name="oper_i") # operand
 
         # create read/write and other scoreboard signalling
         self.rd = go_record(n_src, name="rd") # read in, req out
@@ -205,7 +205,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         m.d.sync += req_l.r.eq(reset_w)
 
         # create a latch/register for the operand
-        oper_r = self.opsubsetkls()
+        oper_r = self.opsubsetkls(name="oper_r")
         latchregister(m, self.oper_i, oper_r, self.issue_i, "oper_l")
 
         # and for each output from the ALU

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index 048e5b4ca9632b5bf8d4ca10b4a79a38bc497f22..1f2845ac96fdc1af37644423204c643b7217f409 100644 (file)
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -339,7 +339,7 @@ class LDSTCompUnit(Elaboratable):
         comb += rst_l.r.eq(issue_i)
 
         # create a latch/register for the operand
-        oper_r = CompLDSTOpSubset()  # Dest register
+        oper_r = CompLDSTOpSubset(name="oper_r")  # Dest register
         latchregister(m, self.oper_i, oper_r, self.issue_i, name="oper_l")
 
         # and for LD