if key in self:
res = dict.__getitem__(self, key)
else:
- info = spr_dict[key]
+ if isinstance(key, int):
+ info = spr_dict[key]
+ else:
+ info = spr_byname[key]
dict.__setitem__(self, key, SelectableInt(0, info.length))
res = dict.__getitem__(self, key)
print ("spr returning", key, res)
comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0
comb += self.fast_out.ok.eq(1)
+ # TRAP fast1 = SRR0
+ with m.If(op.internal_op == InternalOp.OP_TRAP):
+ comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0
+ comb += self.fast_out.ok.eq(1)
+
return m
comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
comb += self.fast_out.ok.eq(1)
+ # TRAP fast2 = SRR1
+ with m.If(op.internal_op == InternalOp.OP_TRAP):
+ comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
+ comb += self.fast_out.ok.eq(1)
+
return m
comb += e.read_fast1.eq(dec_a.fast_out)
comb += e.read_fast2.eq(dec_b.fast_out)
comb += e.write_fast1.eq(dec_o.fast_out)
- comb += e.write_fast1.eq(dec_o2.fast_out)
+ comb += e.write_fast2.eq(dec_o2.fast_out)
comb += e.read_cr1.eq(dec_cr_in.cr_bitfield)
comb += e.read_cr2.eq(dec_cr_in.cr_bitfield_b)
if ok:
spr_num = yield dec2.e.write_fast2.data
spr_num = fast_reg_to_spr(spr_num)
- spr_name = spr_dict[spr_num]
- res['fast2'] = sim.spr[spr_name]
+ spr_name = spr_dict[spr_num].SPR
+ res['fast2'] = sim.spr[spr_name].value
def get_wr_fast_spr1(res, sim, dec2):
ok = yield dec2.e.write_fast1.ok
if ok:
spr_num = yield dec2.e.write_fast1.data
spr_num = fast_reg_to_spr(spr_num)
- spr_name = spr_dict[spr_num]
- res['fast1'] = sim.spr[spr_name]
+ spr_name = spr_dict[spr_num].SPR
+ res['fast1'] = sim.spr[spr_name].value
def get_wr_sim_xer_ca(res, sim, dec2):
cry_out = yield dec2.e.output_carry