convert from public static functions/properties for regspecs

to member functions to obtain regspecs
this allows pspec (containing XLEN) to be passed to the regspecs,
which in turn allows them to be dynamically set by issuer_verilog.py
and unit tests

diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py
index 1e552ff6f0ed937f06e17295b52574dc776cb409..572ec9a6bcd18c22202f4a100531e6f843975889 100644 (file)
--- a/src/soc/fu/alu/pipe_data.py
+++ b/src/soc/fu/alu/pipe_data.py
@@ -3,30 +3,36 @@ from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
 
 
 class ALUInputData(FUBaseData):
-    regspec = [('INT', 'ra', '0:63'),  # RA
-               ('INT', 'rb', '0:63'),  # RB/immediate
-               ('XER', 'xer_so', '32'),  # XER bit 32: SO
-               ('XER', 'xer_ca', '34,45')]  # XER bit 34/45: CA/CA32
-
     def __init__(self, pspec):
         super().__init__(pspec, False)
         # convenience
         self.a, self.b = self.ra, self.rb
 
+    @property
+    def regspec(self):
+        return [('INT', 'ra', self.intrange),  # RA
+               ('INT', 'rb', self.intrange),  # RB/immediate
+               ('XER', 'xer_so', '32'),  # XER bit 32: SO
+               ('XER', 'xer_ca', '34,45')]  # XER bit 34/45: CA/CA32
+
+
 
 class ALUOutputData(FUBaseData):
-    regspec = [('INT', 'o', '0:63'),
+    def __init__(self, pspec):
+        super().__init__(pspec, True)
+        # convenience
+        self.cr0 = self.cr_a
+
+    @property
+    def regspec(self):
+        return [('INT', 'o', self.intrange),
                ('CR', 'cr_a', '0:3'),
                ('XER', 'xer_ca', '34,45'),  # bit0: ca, bit1: ca32
                ('XER', 'xer_ov', '33,44'),  # bit0: ov, bit1: ov32
                ('XER', 'xer_so', '32')]
 
-    def __init__(self, pspec):
-        super().__init__(pspec, True)
-        # convenience
-        self.cr0 = self.cr_a
 
 
 class ALUPipeSpec(CommonPipeSpec):
-    regspec = (ALUInputData.regspec, ALUOutputData.regspec)
     opsubsetkls = CompALUOpSubset
+    regspecklses = (ALUInputData, ALUOutputData)

diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py
index a2f5bcf2508fa09d00f4e43aaf1e610db8f20142..8a6c0071ee51e347379d7f6ca79d9349cd4246ac 100644 (file)
--- a/src/soc/fu/branch/pipe_data.py
+++ b/src/soc/fu/branch/pipe_data.py
@@ -57,5 +57,5 @@ class BranchOutputData(FUBaseData):
 
 
 class BranchPipeSpec(CommonPipeSpec):
-    regspec = (BranchInputData.regspec, BranchOutputData.regspec)
+    regspecklses = (BranchInputData, BranchOutputData)
     opsubsetkls = CompBROpSubset

diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index 1f6e2097c363bbf4060f815029e396d0bdc7699b..873a09df23e3ee884e2ba6eaad6936994ec58e49 100644 (file)
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -120,7 +120,11 @@ class FunctionUnitBaseSingle(MultiCompUnit):
         # spec (NNNPipeSpec instance)
         pspec = speckls(id_wid=2, parent_pspec=parent_pspec)
         opsubset = pspec.opsubsetkls             # get the operand subset class
-        regspec = pspec.regspec                  # get the regspec
+        rsk = pspec.regspecklses        # get the regspec classes
+        regspec = []
+        for kls in rsk:
+            regspec.append(kls(pspec).regspec)
+        print ("regspecs", regspec)
         alu = pipekls(pspec)                     # create actual NNNBasePipe
         self.pspec = pspec
         super().__init__(regspec, alu, opsubset, name=alu_name)  # MultiCompUnit
@@ -160,10 +164,14 @@ class FunctionUnitBaseMulti(ReservationStations2):
 
         # spec (NNNPipeSpec instance)
         pspec = speckls(id_wid=id_wid, parent_pspec=parent_pspec)
-        opsubset = pspec.opsubsetkls             # get the operand subset class
-        regspec = pspec.regspec                  # get the regspec
-        alu = pipekls(pspec)                # create actual NNNBasePipe
         self.pspec = pspec
+        opsubset = pspec.opsubsetkls        # get the operand subset class
+        rsk = pspec.regspecklses        # get the regspec classes
+        regspec = []
+        for kls in rsk:
+            regspec.append(kls(pspec).regspec)
+        print ("regspecs", regspec)
+        alu = pipekls(pspec)                # create actual NNNBasePipe
         alu_name = self.fnunit.name.lower()
         super().__init__(alu, num_rows, alu_name)   # initialise fan-in/fan-out
         self.cu = []
@@ -284,7 +292,11 @@ class LDSTFunctionUnit(LDSTCompUnit):
         # spec (NNNPipeSpec instance)
         pspec = LDSTPipeSpec(id_wid=2, parent_pspec=parent_pspec)
         opsubset = pspec.opsubsetkls             # get the operand subset class
-        regspec = pspec.regspec                  # get the regspec
+        rsk = pspec.regspecklses        # get the regspec classes
+        regspec = []
+        for kls in rsk:
+            regspec.append(kls(pspec).regspec)
+        print ("regspecs", regspec)
         self.opsubsetkls = opsubset
         super().__init__(pi, regspec, awid, opsubset, name=alu_name)
 

diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index edcad2e9aa6a1c84c53b0e73f5925eea7e981c30..f1c6d349201915764682ae5079cc1753f9c94b10 100644 (file)
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -30,5 +30,5 @@ class CROutputData(FUBaseData):
 
 
 class CRPipeSpec(CommonPipeSpec):
-    regspec = (CRInputData.regspec, CROutputData.regspec)
+    regspecklses = (CRInputData, CROutputData)
     opsubsetkls = CompCROpSubset

diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py
index f79f980691510a430caf995b57ec08b0122f4e51..dd4d1bedc0eecb3fee67632dccd0b04480fd0f72 100644 (file)
--- a/src/soc/fu/div/pipe_data.py
+++ b/src/soc/fu/div/pipe_data.py
@@ -134,7 +134,7 @@ class DivPipeSpec(CommonPipeSpec):
         self.div_pipe_kind = div_pipe_kind
         self.core_config = div_pipe_kind.config.core_config
 
-    regspec = (DivInputData.regspec, DivMulOutputData.regspec)
+    regspecklses = (DivInputData, DivMulOutputData)
     opsubsetkls = CompLogicalOpSubset
 
 

diff --git a/src/soc/fu/ldst/pipe_data.py b/src/soc/fu/ldst/pipe_data.py
index fe45b6e83aecd9f251e65c9662aaac5cab181a43..caf8bf5a15fca0dc01692225738ca70b00ae60bf 100644 (file)
--- a/src/soc/fu/ldst/pipe_data.py
+++ b/src/soc/fu/ldst/pipe_data.py
@@ -32,5 +32,5 @@ class LDSTOutputData(FUBaseData):
 
 
 class LDSTPipeSpec(CommonPipeSpec):
-    regspec = (LDSTInputData.regspec, LDSTOutputData.regspec)
+    regspecklses = (LDSTInputData, LDSTOutputData)
     opsubsetkls = CompLDSTOpSubset

diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py
index 3d9077aaf1721b0aea1bbc65c29023e6d8638164..40a18bc214a6ac6a6a652238ae9c24570a856c07 100644 (file)
--- a/src/soc/fu/logical/pipe_data.py
+++ b/src/soc/fu/logical/pipe_data.py
@@ -40,5 +40,5 @@ class LogicalOutputDataFinal(FUBaseData):
 
 
 class LogicalPipeSpec(CommonPipeSpec):
-    regspec = (LogicalInputData.regspec, LogicalOutputDataFinal.regspec)
+    regspecklses = (LogicalInputData, LogicalOutputDataFinal)
     opsubsetkls = CompLogicalOpSubset

diff --git a/src/soc/fu/mmu/pipe_data.py b/src/soc/fu/mmu/pipe_data.py
index 9cc1ff087dd16c4cbb8d3ae2e6b28950020017b1..7272a2256a3117fa2f554fe617e1eec75d7e1d84 100644 (file)
--- a/src/soc/fu/mmu/pipe_data.py
+++ b/src/soc/fu/mmu/pipe_data.py
@@ -37,5 +37,5 @@ class MMUOutputData(FUBaseData):
 
 
 class MMUPipeSpec(CommonPipeSpec):
-    regspec = (MMUInputData.regspec, MMUOutputData.regspec)
+    regspecklses = (MMUInputData, MMUOutputData)
     opsubsetkls = CompMMUOpSubset

diff --git a/src/soc/fu/mul/pipe_data.py b/src/soc/fu/mul/pipe_data.py
index a55e80d1d335d19bdb1ee04475291aaabc0d06fa..072c5da647451ab77d9938c88664e2becc29e243 100644 (file)
--- a/src/soc/fu/mul/pipe_data.py
+++ b/src/soc/fu/mul/pipe_data.py
@@ -27,5 +27,5 @@ class MulOutputData(FUBaseData):
 
 
 class MulPipeSpec(CommonPipeSpec):
-    regspec = (DivInputData.regspec, DivMulOutputData.regspec)
+    regspecklses = (DivInputData, DivMulOutputData)
     opsubsetkls = CompMULOpSubset

diff --git a/src/soc/fu/pipe_data.py b/src/soc/fu/pipe_data.py
index dc17150c3714f8fed2b0e3ef756fdeefa1e7b9f9..427f5c6a0cdc52a7532a989e432782a9e57f1cb0 100644 (file)
--- a/src/soc/fu/pipe_data.py
+++ b/src/soc/fu/pipe_data.py
@@ -17,12 +17,14 @@ class FUBaseData:
     """
 
     def __init__(self, pspec, output, exc_kls=None):
+        self.pspec = pspec
         self.ctx = PipeContext(pspec)  # context for ReservationStation usage
         self.muxid = self.ctx.muxid
         self.data = []
         self.is_output = output
         # take regspec and create data attributes (in or out)
         # TODO: use widspec to create reduced bit mapping.
+        print (self.regspec)
         for i, (regfile, regname, widspec) in enumerate(self.regspec):
             wid = get_regspec_bitwidth([self.regspec], 0, i)
             if output:
@@ -42,6 +44,11 @@ class FUBaseData:
         if hasattr(self, "exception"):
             yield from self.exception.ports()
 
+    # convenience function to return 0:63 if XLEN=64, 0:31 if XLEN=32 etc.
+    @property
+    def intrange(self):
+        return "0:%d" % (self.pspec.XLEN-1)
+
     def eq(self, i):
         eqs = [self.ctx.eq(i.ctx)]
         assert len(self.data) == len(i.data), \

diff --git a/src/soc/fu/regspec.py b/src/soc/fu/regspec.py
index 6804c593971fab5adcce20ddccaf797439a65e86..f5971aadff87b2cad67b9d6610ee929f2081f11f 100644 (file)
--- a/src/soc/fu/regspec.py
+++ b/src/soc/fu/regspec.py
@@ -39,6 +39,7 @@ def get_regspec_bitwidth(regspec, srcdest, idx):
 class RegSpec:
     def __init__(self, rwid, n_src=None, n_dst=None, name=None):
         self._rwid = rwid
+        print ("RegSpec", rwid)
         if isinstance(rwid, int):
             # rwid: integer (covers all registers)
             self._n_src, self._n_dst = n_src, n_dst

diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py
index fd2336dda5f50c9aed5da5558d7f2eb419dab265..276320dbcaead42bdf79a08098a9207202139a79 100644 (file)
--- a/src/soc/fu/shift_rot/pipe_data.py
+++ b/src/soc/fu/shift_rot/pipe_data.py
@@ -42,5 +42,5 @@ class ShiftRotOutputDataFinal(FUBaseData):
 
 
 class ShiftRotPipeSpec(CommonPipeSpec):
-    regspec = (ShiftRotInputData.regspec, ShiftRotOutputDataFinal.regspec)
+    regspecklses = (ShiftRotInputData, ShiftRotOutputDataFinal)
     opsubsetkls = CompSROpSubset

diff --git a/src/soc/fu/spr/pipe_data.py b/src/soc/fu/spr/pipe_data.py
index a6677750e8f7403d54b3cd4f073e1e81f9d0e3cd..5cc7835e6c0e7c432ac4fc98abb943d530a05827 100644 (file)
--- a/src/soc/fu/spr/pipe_data.py
+++ b/src/soc/fu/spr/pipe_data.py
@@ -42,5 +42,5 @@ class SPROutputData(FUBaseData):
 
 
 class SPRPipeSpec(CommonPipeSpec):
-    regspec = (SPRInputData.regspec, SPROutputData.regspec)
+    regspecklses = (SPRInputData, SPROutputData)
     opsubsetkls = CompSPROpSubset

diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py
index 93a135b81c3056292338bcd65f263897a5e468dc..b9c829bccc1811a1e7e334aba22fc3b09e7a907d 100644 (file)
--- a/src/soc/fu/trap/pipe_data.py
+++ b/src/soc/fu/trap/pipe_data.py
@@ -36,5 +36,5 @@ class TrapOutputData(FUBaseData):
 
 
 class TrapPipeSpec(CommonPipeSpec):
-    regspec = (TrapInputData.regspec, TrapOutputData.regspec)
+    regspecklses = (TrapInputData, TrapOutputData)
     opsubsetkls = CompTrapOpSubset