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first cut at Arty A7 Clock-Reset-Generator with S7 PLL
[ls2.git]
/
Makefile
2022-03-10
Luke Kenneth Casso...
sigh gramWishbone is not WB4-pipeline-burst-compliant
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2022-02-19
Luke Kenneth Casso...
match up dram initialisation parameters
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2022-02-18
Luke Kenneth Casso...
make cpu optional (test purposes), make bios optional,
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2022-02-15
Luke Kenneth Casso...
FLGA_TARGET=verilator not uppercase
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2022-02-14
Luke Kenneth Casso...
add external cpu
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2022-02-14
Luke Kenneth Casso...
convert boot rom to bootmem and get first hello_world...
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2022-02-14
Luke Kenneth Casso...
add first cut of verilator simulation, over from microwatt
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