projects / litex.git / history
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
add Icarus verilog simulation workaround (needed to simulate SATA core)
[litex.git] / build /
2015-01-19 Florent Kermarrecreplace Makefile with make.py (will enable verilog... tree | commitdiff