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adding hyperram for arty a7 and also adding a workaround for some stupid issues
[ls2.git] / coldboot / coldboot.c
2022-03-22 Luke Kenneth Casso... adding hyperram for arty a7 and also adding a workaroun... blob | commitdiff | raw
2022-03-19 Luke Kenneth Casso... move quick read/write test for hyperram in coldboot.c blob | commitdiff | raw | diff to current
2022-03-17 Luke Kenneth Casso... work-in-progress on DDR3 firmware. sigh blob | commitdiff | raw | diff to current
2022-03-10 Luke Kenneth Casso... sigh gramWishbone is not WB4-pipeline-burst-compliant blob | commitdiff | raw | diff to current
2022-02-21 Luke Kenneth Casso... * use readl and writel for accessing memory blob | commitdiff | raw | diff to current
2022-02-20 Luke Kenneth Casso... set RAM base to #defined DRAM_BASE not hard-coded value blob | commitdiff | raw | diff to current
2022-02-19 Luke Kenneth Casso... match up dram initialisation parameters blob | commitdiff | raw | diff to current
2022-02-19 Luke Kenneth Casso... put together coldboot startup firmware blob | commitdiff | raw | diff to current