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remove switches from hyperram iverilog test
[ls2.git] / coldboot /
2022-03-26 Luke Kenneth Casso... add hyperram iverilog runner including s27kl0641.v... tree | commitdiff
2022-03-25 Luke Kenneth Casso... loop-test on hyperram read/write which needs carriage... tree | commitdiff
2022-03-22 Luke Kenneth Casso... adding hyperram for arty a7 and also adding a workaroun... tree | commitdiff
2022-03-19 Luke Kenneth Casso... move quick read/write test for hyperram in coldboot.c tree | commitdiff
2022-03-17 Luke Kenneth Casso... work-in-progress on DDR3 firmware. sigh tree | commitdiff
2022-03-10 Luke Kenneth Casso... sigh gramWishbone is not WB4-pipeline-burst-compliant tree | commitdiff
2022-02-21 Luke Kenneth Casso... lengthen cdelay pauses by a factor of 10 tree | commitdiff
2022-02-21 Luke Kenneth Casso... * use readl and writel for accessing memory tree | commitdiff
2022-02-21 Luke Kenneth Casso... use microwatt mmu powerpc.lds with better stack space tree | commitdiff
2022-02-20 Luke Kenneth Casso... set RAM base to #defined DRAM_BASE not hard-coded value tree | commitdiff
2022-02-19 Luke Kenneth Casso... match up dram initialisation parameters tree | commitdiff
2022-02-19 Luke Kenneth Casso... put together coldboot startup firmware tree | commitdiff