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Separate page faults from physical memory access exceptions
[riscv-tests.git]
/
isa
/
rv32si
/
2017-03-09
Andrew Waterman
Permit flexible dirty-bit behavior
tree
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commitdiff
2016-07-22
Andrew Waterman
Move rv32mi dirty bit test to rv32si
tree
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commitdiff
2016-03-15
Andrew Waterman
Merge branch 'priv-1.9'
tree
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commitdiff
2016-03-10
Andrew Waterman
Add missing rv32mi/rv32si tests
tree
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commitdiff
2016-03-03
Andrew Waterman
Some S-mode tests really only belong in M-mode
tree
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commitdiff
2015-07-05
Andrew Waterman
New M-mode timers
tree
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commitdiff
2015-04-04
Andrew Waterman
Run RV32 tests on spike with --isa=RV32
tree
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commitdiff
2015-03-25
Yunsup Lee
split out S-mode tests and M-mode tests
tree
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commitdiff
2015-03-21
Andrew Waterman
Merge rv64si and rv32si tests
tree
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commitdiff
2015-03-17
Andrew Waterman
Merge [shm]call into ecall, [shm]ret into eret
tree
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commitdiff
2015-03-13
Andrew Waterman
Update to new privileged spec
tree
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commitdiff
2015-02-19
Andrew Waterman
Unify rv32/rv64 timer tests
tree
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commitdiff
2015-01-10
Andrew Waterman
Add LICENSE
tree
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commitdiff
2015-01-03
Andrew Waterman
On misaligned fetch, EPC = branch target, not source
tree
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commitdiff
2014-11-22
Yunsup Lee
relax rv32si timer test a bit
tree
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commitdiff
2014-11-13
Yunsup Lee
remove zscale specific tests
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commitdiff
2014-11-13
Yunsup Lee
make rv32si fault load/store test stronger
tree
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commitdiff
2014-11-13
Yunsup Lee
beef up rv32si tests
tree
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commitdiff
2014-02-11
Adam Izraelevitz
Merge branch 'master' of github.com:ucb-bar/riscv-tests
tree
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commitdiff
2014-02-01
Andrew Waterman
Add rv32si tests, including illegality of shamt[5]
tree
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commitdiff