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Check mtval in rv64mi-p-illegal (#104)
[riscv-tests.git]
/
isa
/
rv64si
/
ma_fetch.S
2017-11-12
Andrew Waterman
Make sure that code is 4-byte aligned before disabling...
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2017-10-30
Richard Xia
Declare trap handlers as global symbols. (#87)
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2017-10-27
Andrew Waterman
Verify that mtval/stval is written correctly on misalig...
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2017-09-12
Tim Newsome
Merge pull request #69 from riscv/multicore
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2017-09-01
Andrew Waterman
Improve ma_fetch test to cover JAL and branches
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2016-07-22
Andrew Waterman
Make ma_fetch test robust against code size changes
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2016-07-12
Andrew Waterman
Remove instruction width assumptions to support RVC
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2016-05-01
Andrew Waterman
ERET -> xRET; new memory map
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2016-03-15
Andrew Waterman
Merge branch 'priv-1.9'
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2016-03-03
Andrew Waterman
Fix ma_fetch to work with or without RVC
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2015-03-25
Yunsup Lee
split out S-mode tests and M-mode tests
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2015-03-21
Andrew Waterman
Merge rv64si and rv32si tests
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