isa/rv64si/ma_fetch.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # ma_fetch.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test misaligned fetch trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64S
  14 RVTEST_CODE_BEGIN
  15
  16 #ifdef __MACHINE_MODE
  17   #define sscratch mscratch
  18   #define sstatus mstatus
  19   #define scause mcause
  20   #define sepc mepc
  21   #define stvec_handler mtvec_handler
  22 #endif
  23
  24 #ifndef __rvc
  25   li TESTNUM, 2
  26   li t1, 0
  27   la t0, 1f
  28   jalr t1, t0, 2
  29 1:
  30   j fail
  31 #endif
  32
  33   // This test should pass, since JALR ignores the target LSB
  34   li TESTNUM, 3
  35   la t0, 1f
  36   jalr t1, t0, 1
  37 1:
  38   j 1f
  39   j fail
  40 1:
  41
  42 #ifndef __rvc
  43   li TESTNUM, 4
  44   li t1, 0
  45   la t0, 3f
  46   jr t0, 3
  47 3:
  48   j fail
  49 #endif
  50
  51   j pass
  52
  53   TEST_PASSFAIL
  54
  55 stvec_handler:
  56   # tests 2 and 4 should trap
  57   li a0, 2
  58   beq TESTNUM, a0, 1f
  59   li a0, 4
  60   beq TESTNUM, a0, 1f
  61   j fail
  62 1:
  63
  64   # verify that return address was not written
  65   bnez t1, fail
  66
  67   # verify trap cause
  68   li a1, CAUSE_MISALIGNED_FETCH
  69   csrr a0, scause
  70   bne a0, a1, fail
  71
  72   # verify that epc == &jalr (== t0 - 4)
  73   csrr a1, sepc
  74   addi t0, t0, -4
  75   bne t0, a1, fail
  76
  77   addi a1, a1, 8
  78   csrw sepc, a1
  79   sret
  80
  81 RVTEST_CODE_END
  82
  83   .data
  84 RVTEST_DATA_BEGIN
  85
  86   TEST_DATA
  87
  88 RVTEST_DATA_END