redirect c_lwsp / c_swsp to x28
[riscv-tests.git] / isa / rv64uc /
2018-11-11 Luke Kenneth Casso... redirect c_lwsp / c_swsp to x28
2018-11-03 Luke Kenneth Casso... add some twin-predication zeroing unit tests on c.mv
2018-10-16 Luke Kenneth Casso... modified VL and MVL CSRs to range from 1-XLEN rather...
2018-10-09 Luke Kenneth Casso... alter unit tests to match change in CSR table format
2018-10-07 Luke Kenneth Casso... add cleanup and comments to sv lwsp pred test
2018-10-07 Luke Kenneth Casso... add predicated version of c.lwsp sv unit test
2018-10-07 Luke Kenneth Casso... add 3rd register to c.swsp
2018-10-07 Luke Kenneth Casso... add 3 registers to sv c.lwsp
2018-10-07 Luke Kenneth Casso... add s.swsp sv test
2018-10-06 Luke Kenneth Casso... add sv c_lwsp unit test
2018-10-05 Luke Kenneth Casso... whoops overwrote x2
2018-10-04 Luke Kenneth Casso... add twin-predicated sv c_mv unit test (no zeroing)
2018-10-04 Luke Kenneth Casso... add sv c.mv twin-predication unit test
2017-11-12 Andrew WatermanMake sure that code is 4-byte aligned before disabling...
2017-08-04 Andrew WatermanImprove RVC test
2016-12-07 Andrew Watermanavoid non-standard predefined macros
2016-09-02 Andrew WatermanMake RVC test fit in 16 KiB
2016-08-08 Megan WachsMerge remote-tracking branch 'origin/master'
2016-07-29 Andrew WatermanAdd RV32 RVC and breakpoint tests
2016-07-29 Andrew WatermanAdd an RVC test