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Add timer interrupt test
[riscv-tests.git]
/
isa
/
rv64ui
/
2014-04-18
Christopher Celio
Added a new test case to REMW.
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2014-02-11
Adam Izraelevitz
Merge branch 'master' of github.com:ucb-bar/riscv-tests
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2014-02-11
Andrew Waterman
Revert to old AUIPC definition
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2014-02-01
Andrew Waterman
Shrink hex dumps
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2014-01-31
Andrew Waterman
Reference TESTNUM instead of x28 directly
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2014-01-16
Andrew Waterman
Make LR/SC test more thorough
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2013-10-19
Yunsup Lee
revamp pt tests as well
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2013-10-19
Yunsup Lee
hwacha virtual tests working
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2013-10-17
Yunsup Lee
add passing physical vector tests back in
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2013-09-21
Andrew Waterman
Re-enable virtual memory tests
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2013-09-21
Andrew Waterman
New AUIPC semantics
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2013-09-11
Andrew Waterman
Add AMOXOR test
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2013-08-24
Andrew Waterman
Reflect changes to ISA
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2013-08-12
Sebastien Mirolo
Merge branch 'master' of git://github.com/ucb-bar/riscv...
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2013-07-26
Andrew Waterman
Remove JALR static hints
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2013-05-16
Yunsup Lee
add failing multiply test
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2013-04-24
Yunsup Lee
cleanup Makefiles in isa
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2013-04-22
Yunsup Lee
initial commit
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