git.libre-soc.org Git - litex.git/history - litex/boards/targets/ulx3s.py

2018-11-12	Florent Kermarrec	targets/ulx3s,versa_ecp5: prjtrellis toolchain renamed...	blob \| commitdiff \| raw
2018-11-12	Florent Kermarrec	targets/ulx3s: for now revert to 25MHz clock/no pll	blob \| commitdiff \| raw \| diff to current
2018-11-12	Florent Kermarrec	Merge branch 'master' of github.com/enjoy-digital/litex	blob \| commitdiff \| raw \| diff to current
2018-11-12	enjoy-digital	Merge pull request #125 from daveshah1/trellis_sdram	blob \| commitdiff \| raw \| diff to current
2018-11-09	Florent Kermarrec	targets/ulx3s: get memtest working by disabling sdram...	blob \| commitdiff \| raw \| diff to current
2018-11-05	David Shah	Debugging ULX3S SDRAM	blob \| commitdiff \| raw \| diff to current
2018-11-02	enjoy-digital	Merge pull request #122 from daveshah1/trellis_ulx3s	blob \| commitdiff \| raw \| diff to current
2018-10-31	David Shah	ulx3s: Connect SDRAM clock	blob \| commitdiff \| raw \| diff to current
2018-10-31	David Shah	Fix Trellis build; ULX3S demo boots to BIOS	blob \| commitdiff \| raw \| diff to current
2018-10-30	Florent Kermarrec	boards/targets/ulx3s: reduce l2_size	blob \| commitdiff \| raw \| diff to current
2018-10-29	Florent Kermarrec	boards/targets: add ulx3s	blob \| commitdiff \| raw \| diff to current