litex_sim: Rework Makefiles to put output files in gateware directory.
[litex.git] / litex / build / sim / verilator.py
2020-04-12 Tim 'mithro' Anselllitex_sim: Rework Makefiles to put output files in...
2020-03-05 enjoy-digitalMerge pull request #410 from antmicro/netv2-edid
2020-03-04 Florent Kermarrecbuild: assume vendor tools are in the PATH and remove...
2020-02-20 Florent Kermarrecbuild/sim: add Verilator FST tracing support.
2019-11-20 enjoy-digitalMerge pull request #309 from antmicro/mmcm-fix
2019-11-15 Florent Kermarrecbuild/sim: cleanup run_as_root
2019-11-15 Vamsi K Vytlabuild/sim/modules: add XGMII 10Gbps ethernet module
2019-06-23 Florent Kermarrecadd CONTRIBUTORS file and add copyright header to all...
2019-06-11 enjoy-digitalMerge pull request #198 from TomKeddie/tomk_20190610_ar...
2019-06-07 Florent Kermarrecbuild/sim: allow configuring verilator optimization...
2019-06-07 Florent Kermarrecbuild/sim: allow defining start/end cycles for tracing
2018-12-21 Florent Kermarrecbuild/sim/verilator: compile sim just before running...
2018-12-20 Tim AnsellMerge pull request #144 from mithro/nextpnr-migen-update
2018-12-20 Florent Kermarrecbuild/sim: handle verilog $finish and if coverage is...
2018-12-16 Tim AnsellMerge pull request #135 from mithro/icestorm-ice40up5k
2018-12-12 Florent Kermarrecbuild/sim/verilator: add support for plaform.sources...
2018-12-09 Florent Kermarrecbuild/sim: add coverage parameter to enable code coverage
2018-11-26 enjoy-digitalMerge pull request #128 from mithro/small-fix
2018-11-20 Florent Kermarrecbuild/sim/verilator: add trace parameter to enable...
2018-10-28 enjoy-digitalMerge branch 'master' into xilinx+yosys
2018-10-27 Florent Kermarrecbuild/sim/verilator: don't use THEADS parameters when...
2018-09-24 Florent Kermarrecsim/verilator: add multithread support (default=1)
2018-09-20 Florent Kermarrectargets/sim: generate analyzer.csv
2018-08-23 Tim AnsellMerge pull request #91 from cr1901/ignore-fix
2018-08-23 Tim AnsellMerge pull request #92 from cr1901/l2-gate
2018-08-22 Florent Kermarrecsim: run as root only when needed (ethernet module...
2018-08-16 Florent Kermarrecsim/verilator: catch ctrl-c on exit and revert default...
2018-02-23 Florent Kermarrecreplace litex.gen imports with migen imports
2018-02-19 enjoy-digitalMerge pull request #60 from q3k/for-upstream/top-level...
2018-02-10 enjoy-digitalMerge pull request #57 from rohitk-singh/master
2018-01-24 Paul SchulzMerge branch 'master' of https://github.com/enjoy-digit...
2018-01-23 Florent Kermarrecsim: rename top module to dut and use --top-module...
2018-01-23 Sergiusz BazanskiBuild top module as 'dut' in Verilator and set it as...
2017-06-28 Florent Kermarreclitex/build/sim: rename c functions from lambdasim...
2017-06-28 Pierre-Olivier Vauboinlitex/build/sim: introduce new simulator with modules...
2016-05-04 Florent Kermarrecbuid/sim: add vga framebuffer with SDL
2016-04-19 enjoy-digitalMerge pull request #2 from mithro/master
2016-04-19 Tim 'mithro' AnsellMake verilator build output error messages.
2016-04-12 Florent KermarrecMerge branch 'master' of https://github.com/enjoy-digit...
2016-04-07 Florent Kermarrecbuild/sim: adapt verilator simulation to new stream...
2015-12-02 Florent Kermarrecbuild/sim/verilator: add toolchain_path parameter
2015-11-13 Florent Kermarrecfor now use our fork of migen (to be able to simulate...
2015-11-11 Florent Kermarrecavoid forking migen, we will add custom modules in...
2015-11-07 Florent Kermarreclitex: get verilator simulation working and add sim...
2015-11-07 Florent Kermarreclitex: reorganize things, first work working version