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litex_sim: Rework Makefiles to put output files in gateware directory.
[litex.git]
/
litex
/
build
/
sim
/
verilator.py
2020-04-12
Tim 'mithro' Ansell
litex_sim: Rework Makefiles to put output files in...
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2020-03-05
enjoy-digital
Merge pull request #410 from antmicro/netv2-edid
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2020-03-04
Florent Kermarrec
build: assume vendor tools are in the PATH and remove...
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2020-02-20
Florent Kermarrec
build/sim: add Verilator FST tracing support.
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2019-11-20
enjoy-digital
Merge pull request #309 from antmicro/mmcm-fix
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2019-11-15
Florent Kermarrec
build/sim: cleanup run_as_root
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2019-11-15
Vamsi K Vytla
build/sim/modules: add XGMII 10Gbps ethernet module
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2019-06-23
Florent Kermarrec
add CONTRIBUTORS file and add copyright header to all...
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2019-06-11
enjoy-digital
Merge pull request #198 from TomKeddie/tomk_20190610_ar...
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2019-06-07
Florent Kermarrec
build/sim: allow configuring verilator optimization...
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2019-06-07
Florent Kermarrec
build/sim: allow defining start/end cycles for tracing
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2018-12-21
Florent Kermarrec
build/sim/verilator: compile sim just before running...
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2018-12-20
Tim Ansell
Merge pull request #144 from mithro/nextpnr-migen-update
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2018-12-20
Florent Kermarrec
build/sim: handle verilog $finish and if coverage is...
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2018-12-16
Tim Ansell
Merge pull request #135 from mithro/icestorm-ice40up5k
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2018-12-12
Florent Kermarrec
build/sim/verilator: add support for plaform.sources...
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2018-12-09
Florent Kermarrec
build/sim: add coverage parameter to enable code coverage
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2018-11-26
enjoy-digital
Merge pull request #128 from mithro/small-fix
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2018-11-20
Florent Kermarrec
build/sim/verilator: add trace parameter to enable...
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2018-10-28
enjoy-digital
Merge branch 'master' into xilinx+yosys
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2018-10-27
Florent Kermarrec
build/sim/verilator: don't use THEADS parameters when...
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2018-09-24
Florent Kermarrec
sim/verilator: add multithread support (default=1)
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2018-09-20
Florent Kermarrec
targets/sim: generate analyzer.csv
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2018-08-23
Tim Ansell
Merge pull request #91 from cr1901/ignore-fix
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2018-08-23
Tim Ansell
Merge pull request #92 from cr1901/l2-gate
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2018-08-22
Florent Kermarrec
sim: run as root only when needed (ethernet module...
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2018-08-16
Florent Kermarrec
sim/verilator: catch ctrl-c on exit and revert default...
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2018-02-23
Florent Kermarrec
replace litex.gen imports with migen imports
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2018-02-19
enjoy-digital
Merge pull request #60 from q3k/for-upstream/top-level...
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2018-02-10
enjoy-digital
Merge pull request #57 from rohitk-singh/master
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2018-01-24
Paul Schulz
Merge branch 'master' of https://github.com/enjoy-digit...
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2018-01-23
Florent Kermarrec
sim: rename top module to dut and use --top-module...
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2018-01-23
Sergiusz Bazanski
Build top module as 'dut' in Verilator and set it as...
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2017-06-28
Florent Kermarrec
litex/build/sim: rename c functions from lambdasim...
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2017-06-28
Pierre-Olivier Vauboin
litex/build/sim: introduce new simulator with modules...
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2016-05-04
Florent Kermarrec
buid/sim: add vga framebuffer with SDL
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2016-04-19
enjoy-digital
Merge pull request #2 from mithro/master
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2016-04-19
Tim 'mithro' Ansell
Make verilator build output error messages.
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2016-04-12
Florent Kermarrec
Merge branch 'master' of https://github.com/enjoy-digit...
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2016-04-07
Florent Kermarrec
build/sim: adapt verilator simulation to new stream...
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2015-12-02
Florent Kermarrec
build/sim/verilator: add toolchain_path parameter
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2015-11-13
Florent Kermarrec
for now use our fork of migen (to be able to simulate...
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2015-11-11
Florent Kermarrec
avoid forking migen, we will add custom modules in...
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2015-11-07
Florent Kermarrec
litex: get verilator simulation working and add sim...
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2015-11-07
Florent Kermarrec
litex: reorganize things, first work working version
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