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soc/interconnect/stream: set packetized to True by default (we are going to remove...
[litex.git] / litex / build /
2016-02-17 Florent Kermarrecbuild/xilinx: cleanup Vivado/ISE special_overrides tree | commitdiff
2016-02-11 Florent Kermarrecgen/build: use verilog 2001-style synthesis attributes... tree | commitdiff
2015-12-09 Florent Kermarrecbuild/xilinx/vivado: use build_name as top in synth_design tree | commitdiff
2015-12-02 Florent Kermarrecbuild/sim/verilator: add toolchain_path parameter tree | commitdiff
2015-12-02 Florent Kermarrecbuild: pass build_name to get_verilog (same name for... tree | commitdiff
2015-11-30 Florent Kermarrecgen/build: use name_override for all IOs defined in... tree | commitdiff
2015-11-30 Florent Kermarrecbuild: ensure we return to working directory after... tree | commitdiff
2015-11-19 Florent Kermarrecbuild/generic_platform: add support for int parameter... tree | commitdiff
2015-11-16 Florent Kermarrecbuild: remove edif support tree | commitdiff
2015-11-13 Florent Kermarrecfor now use our fork of migen (to be able to simulate... tree | commitdiff
2015-11-11 Florent Kermarrecavoid forking migen, we will add custom modules in... tree | commitdiff
2015-11-10 Florent Kermarrecboards/targets/sim: get SDRAM working in simulation... tree | commitdiff
2015-11-10 Florent Kermarreclitex/build/xilinx/programmer: remove UrJTAG and Adept tree | commitdiff
2015-11-07 Florent Kermarreclitex: get verilator simulation working and add sim... tree | commitdiff
2015-11-07 Florent Kermarreclitex: reorganize things, first work working version tree | commitdiff