gen/fhdl/verilog: list available clock domains on keyerror
[litex.git] / litex / gen / fhdl / verilog.py
2017-06-05 Florent Kermarrecgen/fhdl/verilog: list available clock domains on keyerror
2017-01-17 enjoy-digitalMerge pull request #14 from mithro/spiflash2
2017-01-13 Florent Kermarrecmerge most of misoc 54e1ef82 and migen e93d0601 changes
2016-04-29 Florent Kermarrecgen/fhdl: add Display for debug in simulation
2016-04-27 Florent Kermarrecgen/fhdl/verilog: add do in reserved_keywords
2016-03-21 Florent Kermarrecgen/build: merge with migen 0575c749e35a7180f0dca408e42...
2016-02-11 Florent Kermarrecgen/build: use verilog 2001-style synthesis attributes...
2015-12-02 Florent Kermarrecgen/fhdl/verilog: add regular comb parameter to allow...
2015-11-16 Florent Kermarrecgen/fhdl/verilog: remove asic_syntax and expose reg_ini...
2015-11-14 Florent Kermarrecadd TODOs
2015-11-13 Florent Kermarrecfor now use our fork of migen (to be able to simulate...
2015-11-13 Florent Kermarreclitex/gen: reintegrate migen with modifications to...
2015-11-11 Florent Kermarrecavoid forking migen, we will add custom modules in...
2015-11-07 Florent Kermarreclitex: reorganize things, first work working version