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gen/fhdl/verilog: list available clock domains on keyerror
[litex.git]
/
litex
/
gen
/
fhdl
/
verilog.py
2017-06-05
Florent Kermarrec
gen/fhdl/verilog: list available clock domains on keyerror
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2017-01-17
enjoy-digital
Merge pull request #14 from mithro/spiflash2
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2017-01-13
Florent Kermarrec
merge most of misoc 54e1ef82 and migen e93d0601 changes
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2016-04-29
Florent Kermarrec
gen/fhdl: add Display for debug in simulation
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2016-04-27
Florent Kermarrec
gen/fhdl/verilog: add do in reserved_keywords
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2016-03-21
Florent Kermarrec
gen/build: merge with migen 0575c749e35a7180f0dca408e42...
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2016-02-11
Florent Kermarrec
gen/build: use verilog 2001-style synthesis attributes...
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2015-12-02
Florent Kermarrec
gen/fhdl/verilog: add regular comb parameter to allow...
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2015-11-16
Florent Kermarrec
gen/fhdl/verilog: remove asic_syntax and expose reg_ini...
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2015-11-14
Florent Kermarrec
add TODOs
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2015-11-13
Florent Kermarrec
for now use our fork of migen (to be able to simulate...
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2015-11-13
Florent Kermarrec
litex/gen: reintegrate migen with modifications to...
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2015-11-11
Florent Kermarrec
avoid forking migen, we will add custom modules in...
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2015-11-07
Florent Kermarrec
litex: reorganize things, first work working version
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