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[litex.git] / litex / gen / fhdl /
2020-05-12 enjoy-digitalMerge pull request #478 from antmicro/extended_spi_flash tree | commitdiff
2020-05-11 enjoy-digitalMerge branch 'master' into rdimm_bside_init tree | commitdiff
2020-05-11 enjoy-digitalMerge pull request #484 from ilya-epifanov/lattice... tree | commitdiff
2020-05-11 enjoy-digitalMerge branch 'master' into cpu-imac-config-for-vexriscv tree | commitdiff
2020-05-07 Dave MarplesMerge branch 'master' of https://github.com/enjoy-digit... tree | commitdiff
2020-05-05 Florent Kermarrecgen/fhdl/verilog: explicitly define input/output/inout... tree | commitdiff
2020-01-12 Florent Kermarrecgen/fhdl/verilog: fix signed init values tree | commitdiff
2020-01-09 enjoy-digitalMerge pull request #337 from gregdavill/spi-flash tree | commitdiff
2019-12-21 enjoy-digitalMerge pull request #321 from gsomlo/gls-rocket-aximem... tree | commitdiff
2019-12-21 enjoy-digitalMerge pull request #319 from DurandA/feature-integer... tree | commitdiff
2019-12-19 Arnaud DurandAdd integer attributes tree | commitdiff
2019-12-19 Arnaud DurandRevert "gen/fhdl/verilog: allow single element verilog... tree | commitdiff
2019-08-31 enjoy-digitalMerge pull request #251 from micro-FPGA/master tree | commitdiff
2019-08-28 Florent Kermarrecgen/fhdl/verilog: allow single element verilog inline... tree | commitdiff
2019-06-23 Florent Kermarrecadd CONTRIBUTORS file and add copyright header to all... tree | commitdiff
2019-04-23 enjoy-digitalMerge pull request #171 from keesj/develop_as_user tree | commitdiff
2019-04-23 Florent Kermarrecsoc/integration: also add sha-1/date to generated softw... tree | commitdiff
2019-04-23 Florent Kermarrecbuild: add sha-1/date to generated verilog, change... tree | commitdiff
2018-12-16 Tim AnsellMerge pull request #135 from mithro/icestorm-ice40up5k tree | commitdiff
2018-12-09 Florent Kermarrecgen/fhdl: add simulation Display, Finish support. tree | commitdiff
2018-12-04 Florent Kermarrecgen: integrate migen changes tree | commitdiff
2018-10-30 Florent Kermarrecbuild/lattice/prjtrellis: modify generated verilog... tree | commitdiff
2018-10-29 Florent KermarrecMerge branch 'master' of github.com/enjoy-digital/litex tree | commitdiff
2018-10-29 Florent Kermarrecgen/fhdl/verilog: set direction to io signals tree | commitdiff
2018-05-01 Florent Kermarrecbuild: use our own fhdl/verilog code (needed to avoid... tree | commitdiff
2018-02-23 Florent Kermarrecreplace litex.gen imports with migen imports tree | commitdiff
2018-02-23 Florent Kermarrecremove migen fork from litex tree | commitdiff
2018-02-10 enjoy-digitalMerge pull request #57 from rohitk-singh/master tree | commitdiff
2018-01-23 enjoy-digitalMerge pull request #59 from q3k/for-upstream/multiple... tree | commitdiff
2018-01-23 Sergiusz BazanskiAllow for multiple synthesis directives in specials. tree | commitdiff
2017-12-30 enjoy-digitalMerge pull request #40 from mithro/or1k-linux tree | commitdiff
2017-12-30 enjoy-digitalMerge pull request #41 from cr1901/python-3.6 tree | commitdiff
2017-12-30 William D. Jonesfhdl/tracer: Import Python 3.5/3.6 version guards from... tree | commitdiff
2017-09-26 enjoy-digitalMerge pull request #28 from enjoy-digital/eb-docs-2 tree | commitdiff
2017-09-13 Florent Kermarrecgen/fhdl/verilog: revert _printcomb_simulation and... tree | commitdiff
2017-06-28 Florent Kermarrecmerge migen 9a6fdea3 changes tree | commitdiff
2017-06-10 Florent Kermarrecgen/fhdl/specials: revert migen's commit d98502c6 ... tree | commitdiff
2017-06-05 Florent Kermarrecgen/fhdl/verilog: list available clock domains on keyerror tree | commitdiff
2017-01-17 enjoy-digitalMerge pull request #14 from mithro/spiflash2 tree | commitdiff
2017-01-13 Florent Kermarrecmerge most of misoc 54e1ef82 and migen e93d0601 changes tree | commitdiff
2016-05-18 Florent Kermarrecgen/fhdl/structure: fix Display tree | commitdiff
2016-04-29 Florent Kermarrecgen/fhdl: add Display for debug in simulation tree | commitdiff
2016-04-27 Florent Kermarrecgen/fhdl/verilog: add do in reserved_keywords tree | commitdiff
2016-03-23 Florent Kermarrecgen/sim, fhdl: remove port.we_granularity limitation... tree | commitdiff
2016-03-21 Florent Kermarrecgen/build: merge with migen 0575c749e35a7180f0dca408e42... tree | commitdiff
2016-02-11 Florent Kermarrecgen/build: use verilog 2001-style synthesis attributes... tree | commitdiff
2015-12-02 Florent Kermarrecgen/fhdl/verilog: add regular comb parameter to allow... tree | commitdiff
2015-11-16 Florent Kermarrecbuild: remove edif support tree | commitdiff
2015-11-16 Florent Kermarrecgen/fhdl/verilog: remove asic_syntax and expose reg_ini... tree | commitdiff
2015-11-14 Florent Kermarrecadd TODOs tree | commitdiff
2015-11-13 Florent Kermarrecfor now use our fork of migen (to be able to simulate... tree | commitdiff
2015-11-13 Florent Kermarreclitex/gen: reintegrate migen with modifications to... tree | commitdiff
2015-11-11 Florent Kermarrecavoid forking migen, we will add custom modules in... tree | commitdiff
2015-11-07 Florent Kermarreclitex: reorganize things, first work working version tree | commitdiff