minor change in BP top module
[litex.git] / litex / gen / sim /
2019-06-23 Florent Kermarrecadd CONTRIBUTORS file and add copyright header to all...
2018-12-16 Tim AnsellMerge pull request #135 from mithro/icestorm-ice40up5k
2018-12-09 Florent Kermarrecgen/sim/core: add args support on Display
2018-12-04 Florent Kermarrecgen: integrate migen changes
2018-04-04 Florent Kermarrecgen/sim: fix import to use litex simulator instead...
2018-02-23 Florent Kermarrecreplace litex.gen imports with migen imports
2017-06-28 Florent Kermarrecmerge migen 9a6fdea3 changes
2017-04-25 Florent Kermarrecgen/sim/core: do not use reset_less clock_domains for...
2017-01-17 enjoy-digitalMerge pull request #14 from mithro/spiflash2
2017-01-13 Florent Kermarrecmerge most of misoc 54e1ef82 and migen e93d0601 changes
2016-05-28 Florent Kermarrecgen/sim/vcd: allow continous update of vcd file and...
2016-05-18 Florent Kermarrecgen/sim/core: add Display support
2016-03-25 Florent Kermarrecgen/sim: hack to update vcd output file during simulati...
2016-03-23 Florent Kermarrecgen/sim, fhdl: remove port.we_granularity limitation...
2016-03-21 Florent Kermarrecgen: add missing sim files
2016-03-21 Florent Kermarrecgen/build: merge with migen 0575c749e35a7180f0dca408e42...
2015-12-02 Florent Kermarrecgen/fhdl/verilog: add regular comb parameter to allow...
2015-11-13 Florent Kermarreclitex/gen: reintegrate migen with modifications to...
2015-11-11 Florent Kermarrecavoid forking migen, we will add custom modules in...
2015-11-07 Florent Kermarreclitex: reorganize things, first work working version