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gen/genlib/record: fix connect
[litex.git] / litex / gen / sim /
2016-03-25 Florent Kermarrecgen/sim: hack to update vcd output file during simulati... tree | commitdiff
2016-03-23 Florent Kermarrecgen/sim, fhdl: remove port.we_granularity limitation... tree | commitdiff
2016-03-21 Florent Kermarrecgen: add missing sim files tree | commitdiff
2016-03-21 Florent Kermarrecgen/build: merge with migen 0575c749e35a7180f0dca408e42... tree | commitdiff
2015-12-02 Florent Kermarrecgen/fhdl/verilog: add regular comb parameter to allow... tree | commitdiff
2015-11-13 Florent Kermarreclitex/gen: reintegrate migen with modifications to... tree | commitdiff
2015-11-11 Florent Kermarrecavoid forking migen, we will add custom modules in... tree | commitdiff
2015-11-07 Florent Kermarreclitex: reorganize things, first work working version tree | commitdiff