add openFPGAloader programmer
[litex.git] / litex / gen /
2020-07-22 enjoy-digitalMerge pull request #599 from antmicro/gen-mmcm-pr
2020-07-10 enjoy-digitalMerge pull request #587 from antmicro/mor1x_ror_instruction
2020-07-07 Florent Kermarreclitex/gen: remove io that has been replaced with litex...
2020-05-12 enjoy-digitalMerge pull request #478 from antmicro/extended_spi_flash
2020-05-11 enjoy-digitalMerge branch 'master' into rdimm_bside_init
2020-05-11 enjoy-digitalMerge pull request #484 from ilya-epifanov/lattice...
2020-05-11 enjoy-digitalMerge branch 'master' into cpu-imac-config-for-vexriscv
2020-05-07 Dave MarplesMerge branch 'master' of https://github.com/enjoy-digit...
2020-05-05 Florent Kermarrecgen/fhdl/verilog: explicitly define input/output/inout...
2020-04-10 Florent Kermarreclitex/build: move io.py from litex/gen and re-import...
2020-04-09 Florent Kermarreclitex/gen: add io with SDRInput/SDROutput (if not overr...
2020-01-12 Florent Kermarrecgen/fhdl/verilog: fix signed init values
2020-01-09 enjoy-digitalMerge pull request #337 from gregdavill/spi-flash
2019-12-21 enjoy-digitalMerge pull request #321 from gsomlo/gls-rocket-aximem...
2019-12-21 enjoy-digitalMerge pull request #319 from DurandA/feature-integer...
2019-12-19 Arnaud DurandAdd integer attributes
2019-12-19 Arnaud DurandRevert "gen/fhdl/verilog: allow single element verilog...
2019-08-31 enjoy-digitalMerge pull request #251 from micro-FPGA/master
2019-08-28 Florent Kermarrecgen/fhdl/verilog: allow single element verilog inline...
2019-06-23 Florent Kermarrecadd CONTRIBUTORS file and add copyright header to all...
2019-04-23 enjoy-digitalMerge pull request #171 from keesj/develop_as_user
2019-04-23 Florent Kermarrecsoc/integration: also add sha-1/date to generated softw...
2019-04-23 Florent Kermarrecbuild: add sha-1/date to generated verilog, change...
2018-12-16 Tim AnsellMerge pull request #135 from mithro/icestorm-ice40up5k
2018-12-09 Florent Kermarrecgen/sim/core: add args support on Display
2018-12-09 Florent Kermarrecgen/fhdl: add simulation Display, Finish support.
2018-12-04 Florent Kermarrecgen: integrate migen changes
2018-10-30 Florent Kermarrecgen: add common with reverse_bits/reverse_bytes functions
2018-10-30 Florent Kermarrecbuild/lattice/prjtrellis: modify generated verilog...
2018-10-29 Florent KermarrecMerge branch 'master' of github.com/enjoy-digital/litex
2018-10-29 Florent Kermarrecgen/fhdl/verilog: set direction to io signals
2018-05-01 Florent Kermarrecbuild: use our own fhdl/verilog code (needed to avoid...
2018-04-04 Florent Kermarrecgen/sim: fix import to use litex simulator instead...
2018-02-23 Florent Kermarrecreplace litex.gen imports with migen imports
2018-02-23 Florent Kermarrecremove migen fork from litex
2018-02-10 enjoy-digitalMerge pull request #57 from rohitk-singh/master
2018-01-23 enjoy-digitalMerge pull request #59 from q3k/for-upstream/multiple...
2018-01-23 Sergiusz BazanskiAllow for multiple synthesis directives in specials.
2017-12-30 enjoy-digitalMerge pull request #40 from mithro/or1k-linux
2017-12-30 enjoy-digitalMerge pull request #41 from cr1901/python-3.6
2017-12-30 William D. Jonesfhdl/tracer: Import Python 3.5/3.6 version guards from...
2017-09-26 enjoy-digitalMerge pull request #28 from enjoy-digital/eb-docs-2
2017-09-13 Florent Kermarrecgen/fhdl/verilog: revert _printcomb_simulation and...
2017-07-24 Florent Kermarrecgen/genlib/cdc/gearbox: fix possible pointers overlap...
2017-07-04 Florent Kermarrecmerge migen ee0e709 changes
2017-06-28 Florent Kermarrecsoc/interconnect/stream: use reset_less attr of signal...
2017-06-28 Florent Kermarrecmerge migen 9a6fdea3 changes
2017-06-10 Florent Kermarrecgen/fhdl/specials: revert migen's commit d98502c6 ...
2017-06-05 Florent Kermarrecgen/fhdl/verilog: list available clock domains on keyerror
2017-06-01 Florent Kermarrecgen/genlib/cdc/gearbox: remove TODO since code is alrea...
2017-05-31 Florent Kermarrecgen/genlib/cdc/gearbox: add more margin on pointers...
2017-04-25 Florent Kermarrecgen/genlib/cdc: cleanup lcm computation, fix timeout...
2017-04-25 Florent Kermarrecgen/sim/core: do not use reset_less clock_domains for...
2017-04-25 Florent Kermarrecgen/genlib/cdc: import gcd from math and not fractions...
2017-04-24 Florent Kermarreclitex/gen/util/misc: import gcd from math and not fract...
2017-04-19 Florent Kermarrecgen/genlib/misc: add BitSlip
2017-04-19 Florent Kermarrecgen/genlib/cdc: add gearbox
2017-01-17 enjoy-digitalMerge pull request #14 from mithro/spiflash2
2017-01-13 Florent Kermarrecmerge most of misoc 54e1ef82 and migen e93d0601 changes
2017-01-12 enjoy-digitalMerge pull request #15 from joeladdison/master
2017-01-12 Florent Kermarrecgen/genlib/cdc: add GrayDecoder from misoc
2016-10-14 Robert JordensElasticBuffer: infer reset
2016-10-13 Florent Kermarrecgen/genlib/cdc: add ElasticBuffer
2016-05-28 Florent Kermarrecgen/sim/vcd: allow continous update of vcd file and...
2016-05-18 Florent Kermarrecgen/sim/core: add Display support
2016-05-18 Florent Kermarrecgen/fhdl/structure: fix Display
2016-04-29 Florent Kermarrecgen/fhdl: add Display for debug in simulation
2016-04-27 Florent Kermarrecgen/fhdl/verilog: add do in reserved_keywords
2016-04-21 Florent Kermarrecgen/genlib/record: fix connect
2016-04-21 Florent Kermarrecgen/genlib/record: fix connect
2016-04-21 Florent Kermarrecgen/genlib/record: rename leave_out by omit and add...
2016-03-25 Florent Kermarrecgen/sim: hack to update vcd output file during simulati...
2016-03-23 Florent Kermarrecgen/sim, fhdl: remove port.we_granularity limitation...
2016-03-21 Florent Kermarrecgen: add missing sim files
2016-03-21 Florent Kermarrecgen: remove vpi (no longer used)
2016-03-21 Florent Kermarrecgen/build: merge with migen 0575c749e35a7180f0dca408e42...
2016-02-11 Florent Kermarrecgen/build: use verilog 2001-style synthesis attributes...
2015-12-02 Florent Kermarrecgen/fhdl/verilog: add regular comb parameter to allow...
2015-11-30 Florent Kermarrecgen/build: use name_override for all IOs defined in...
2015-11-16 Florent Kermarrecbuild: remove edif support
2015-11-16 Florent Kermarrecgen/fhdl/verilog: remove asic_syntax and expose reg_ini...
2015-11-14 Florent Kermarrecadd TODOs
2015-11-13 Florent Kermarrecfor now use our fork of migen (to be able to simulate...
2015-11-13 Florent Kermarreclitex/gen: reintegrate migen with modifications to...
2015-11-11 Florent Kermarrecavoid forking migen, we will add custom modules in...
2015-11-07 Florent Kermarreclitex: reorganize things, first work working version
2015-11-07 Florent Kermarrecimport migen in litex/gen