soc/cores/clock: add Max10PLL.
[litex.git] / litex / soc / cores / clock.py
2020-04-08 Florent Kermarrecsoc/cores/clock: add Max10PLL.
2020-04-08 Florent Kermarrecsoc/cores/clock: add Cyclone10LPPLL.
2020-04-08 Florent Kermarrecsoc/cores/clock/CycloneVPLL: fix typos.
2020-04-08 Florent Kermarrecsoc/cores/clock: rename Altera to Intel.
2020-04-07 Florent Kermarrecsoc/cores/clock: add CycloneVPLL.
2020-04-07 Florent Kermarrecsoc/cores/clock: add initial AlteraClocking/CycloneIV...
2020-04-06 Florent Kermarrecsoc/cores: use reset_less on datapath/configuration...
2020-04-03 Florent Kermarrecsoc/cores/clock/ECP5PLL: add CLKI_DIV support.
2020-03-25 enjoy-digitalMerge pull request #437 from feliks-montez/bugfix/fix...
2020-03-24 Florent Kermarreccores/clock/ECP5PLL: add phase support.
2020-03-19 enjoy-digitalMerge pull request #431 from antmicro/hybrid-mac
2020-03-16 Florent Kermarrecsoc/cores/clock: make sure specific clkoutn_divide_rang...
2020-03-13 enjoy-digitalMerge pull request #427 from enjoy-digital/s7mmcm_fract...
2020-03-13 Florent Kermarreccores/clock: simplify Fractional Divide support on...
2020-03-13 enjoy-digitalMerge pull request #421 from betrusted-io/clk0_fractional
2020-03-13 Florent Kermarrectest: add initial (minimal) test for clock abstraction...
2020-03-11 Sean CrossMerge pull request #422 from xobs/core-doc-fixes
2020-03-10 Florent Kermarreccores/clock/USIDELAYCTRL: use separate reset/ready...
2020-03-10 bunnieadd fractional division options to clk0 config on PLL
2020-03-10 enjoy-digitalMerge pull request #419 from gsomlo/gls-ultra-sdram...
2020-03-10 Florent Kermarreccores/clock: add logging to visualize clkin/clkouts...
2020-03-09 Florent Kermarrecsoc/cores/clock/iCE40PLL: add SB_PLL40_PAD support.
2020-02-24 enjoy-digitalMerge pull request #400 from Xiretza/ecp5-pll-freqfix
2020-02-24 XiretzaFix ECP5PLL VCO frequency range
2020-02-18 Florent Kermarrecsoc/cores/clock: add reset_cycles parameter to S7IDELAY...
2020-02-08 enjoy-digitalMerge pull request #278 from scanakci/blackparrot_litex
2020-01-24 enjoy-digitalMerge pull request #358 from antmicro/litex_sim_ddr
2020-01-24 Florent Kermarreccores/clock/create_clkout: rename clk_ce to ce, improve...
2020-01-24 enjoy-digitalMerge pull request #357 from betrusted-io/add_clk_ce
2020-01-24 bunnieadd BUFIO to clockgen buffer options
2020-01-24 bunnieadd option for BUFGCE to the clock generator buffer...
2020-01-19 bunniecores/clock/xadc: ease DRP timings
2020-01-09 enjoy-digitalMerge pull request #337 from gregdavill/spi-flash
2020-01-06 enjoy-digitalMerge pull request #331 from betrusted-io/xadc_mods
2020-01-01 Florent Kermarrecsoc/cores/clock: also allow margin=0 on iCE40PLL and...
2020-01-01 enjoy-digitalMerge pull request #328 from betrusted-io/precise_clocks
2020-01-01 bunnieadd the possibility for a "precise" clock solution
2019-11-20 Florent Kermarrecsoc/cores/clock: change drp_locked to CSRStatus and...
2019-11-20 Florent Kermarrecsoc/cores/clock: reset PLL/MMCM on all 7-series/Ultrasc...
2019-11-20 enjoy-digitalMerge pull request #309 from antmicro/mmcm-fix
2019-11-20 Pawel Czarneckisoc/cores/clock: add lock reg and assign reset
2019-10-01 enjoy-digitalMerge pull request #269 from antmicro/rework_icap
2019-09-29 Florent Kermarrecsoc/cores/clocks: improve readibility
2019-08-09 Florent Kermarreccores/clock/S7PLL: fix -1/-3 speedgrade vco max freq...
2019-08-07 Florent Kermarreccores/clock: juse use 1e9/freq instead of period_ns
2019-08-07 Florent Kermarreccores/clock/s6pll: add phase support
2019-08-07 Florent Kermarreccores/clock/xilinx: change clkfbout_mult loop order...
2019-07-23 Florent Kermarreccores/clock: cleanup
2019-07-23 Florent Kermarreccores/clock: add initial iCE40 support
2019-07-22 enjoy-digitalMerge pull request #216 from antmicro/booting_vexriscv_...
2019-07-16 enjoy-digitalMerge pull request #219 from flammit/fix-ecp5-pll
2019-07-14 Francis Lamsoc: cores: fix name of EHXPLLL output clock in ECP5PLL
2019-06-23 Florent Kermarrecadd CONTRIBUTORS file and add copyright header to all...
2019-04-23 Florent Kermarreccores/clock: add divclk_divide_range on S6PLL/S6DCM
2019-04-23 Florent Kermarreccores/clock: use common XilinxClocking class for all...
2019-04-23 Michael Betzcores/clock: add initial Spartan6 PLL/DCM support
2019-04-19 Sean CrossMerge branch 'master' of https://github.com/enjoy-digit...
2019-04-15 Florent Kermarrecsoc/cores/clock: add divclk_divide/vco_margin support...
2019-04-15 Florent Kermarrecsoc/cores/clock: improve presentation
2019-02-14 Florent Kermarrecsoc/cores/clock: add actual clk_freqs to config
2019-01-22 Florent Kermarrecsoc/cores/clock: add USIDELAYCTRL
2019-01-16 Florent Kermarrecsoc/cores/clock: allow ClockSignal to be used for clkin
2019-01-08 Florent Kermarrecsoc/cores/clock: add Xilinx Ultrascale PLL/MMCM
2018-12-28 Florent Kermarrecsoc/cores/clock/ECP5PLL: add basic phase support
2018-12-20 Tim AnsellMerge pull request #144 from mithro/nextpnr-migen-update
2018-12-19 Florent Kermarrecsoc/cores/clock: remove return on S7PLL.create_clkout
2018-11-27 enjoy-digitalMerge pull request #130 from jfng/master
2018-11-27 Florent Kermarreccores/clock: test and fix ECP5PLL, phase still not...
2018-11-26 enjoy-digitalMerge pull request #128 from mithro/small-fix
2018-11-23 Florent Kermarreccores/clock: add ECP5PLL
2018-11-13 Florent Kermarreccores/clock/S7: just reset the generated clock, not...
2018-11-12 enjoy-digitalMerge pull request #125 from daveshah1/trellis_sdram
2018-11-02 enjoy-digitalMerge pull request #122 from daveshah1/trellis_ulx3s
2018-11-01 enjoy-digitalMerge pull request #123 from cr1901/prv32-min
2018-10-31 Florent Kermarreccores/clock: add with_reset parameter (default to True)
2018-10-28 enjoy-digitalMerge branch 'master' into xilinx+yosys
2018-10-16 Florent Kermarrecsoc/cores/clock: add margin parameter to create_clkout...
2018-09-28 Florent Kermarrecsoc/cores/clock: add expose_drp on S7PLL/S7MMCM
2018-09-25 enjoy-digitalMerge pull request #109 from cr1901/xip-improve
2018-09-25 Florent Kermarrecsoc/cores/clock: different clkin_freq_range for pll...
2018-09-25 Florent Kermarrecsoc/cores/clock: different vco_freq_range for pll and...
2018-09-25 Florent Kermarrecsoc/core/clock: allow selecting buffer type (None,...
2018-09-24 Florent Kermarrecsoc/cores/clock: create specific S7IDELAYCTRL module
2018-09-24 Florent Kermarrecsoc/cores/clock: add S7MMCM support
2018-09-24 Florent Kermarrecsoc/cores/clocks/S7PLL: add speedgrade support, default...
2018-09-24 Florent Kermarrecsoc/cores: init clock abstraction module