soc/integration/soc_core: revert default mem_map (do specific RocketChip remapping...
[litex.git] / litex / soc / integration / soc_core.py
2019-05-24 Florent Kermarrecsoc/integration/soc_core: revert default mem_map (do...
2019-05-24 enjoy-digitalMerge pull request #186 from gsomlo/gls-rocket
2019-05-23 Gabriel L. Somlosoc/cores/cpu/rocket: Support for 64-bit RocketChip...
2019-05-16 Florent KermarrecMerge branch 'master' of github.com/enjoy-digital/litex
2019-05-16 Florent Kermarrecsoc_core: remove csr_expose and add add_csr_master...
2019-05-10 Florent Kermarrecsoc/integration/soc_core: allow user to defined interna...
2019-05-09 Florent Kermarrecsoc/integration/soc_core: rework csr assignation/reserv...
2019-05-09 Florent KermarrecMerge branch 'master' of github.com/enjoy-digital/litex
2019-05-09 Florent Kermarrecintegration/soc_core: rework interrupt assignation...
2019-05-03 Florent Kermarrecsoc/get_mem_data: add direct support for regions
2019-04-29 Florent Kermarrecintegration/soc_core: use cpu name as cpu-type for...
2019-04-27 enjoy-digitalMerge pull request #175 from mithro/cpu-docs
2019-04-26 Tim 'mithro' AnsellAdding testing of cpu variants.
2019-04-26 Tim 'mithro' AnsellWork with no `cpu_variant` provided.
2019-04-26 Tim 'mithro' AnsellStandardize the `cpu_variant` strings.
2019-04-25 Florent Kermarrecsoc/integration/soc_core: fix get_mem_data when not...
2019-04-25 Florent Kermarrecsoc/integration/soc_core: fix get_mem_data for json...
2019-04-25 Florent Kermarrecsoc/integration/soc_core: add integrated_sram_init
2019-04-22 Florent Kermarrecglobal: switch to VexRiscv as the default CPU
2019-04-19 Sean CrossMerge branch 'master' of https://github.com/enjoy-digit...
2019-03-22 enjoy-digitalMerge pull request #154 from daveshah1/yosys_xilinx_edif
2019-03-16 Florent Kermarrecsoc_core/get_mem_data: add json support
2019-01-29 Florent Kermarrecsoc/integration/soc_core: allow disabling wishbone...
2018-11-26 enjoy-digitalMerge pull request #128 from mithro/small-fix
2018-11-21 Florent Kermarrecsoc/integration/soc_core: add csr_map_update function
2018-11-20 Florent Kermarrecsoc_core: convert cpu_type="None" string to None
2018-11-13 Florent Kermarrecsoc_core: check for cpu before checking interrupt
2018-10-28 enjoy-digitalMerge branch 'master' into xilinx+yosys
2018-10-09 enjoy-digitalMerge pull request #116 from stffrdhrn/sim-uart
2018-10-06 Florent Kermarrecsoc_core: add csr range check
2018-10-04 enjoy-digitalMerge pull request #112 from cr1901/8k-b-evn
2018-10-04 enjoy-digitalMerge pull request #113 from stffrdhrn/litex-trivial
2018-10-04 Stafford HorneFix help for or1k builds
2018-09-24 Florent Kermarrecsoc_core: use cpu instead of cpu_or_bridge internally...
2018-09-24 Florent Kermarrecsoc_core/get_mem_data: add endianness support and use...
2018-09-24 Florent Kermarreccores/cpu: add software informations to cpu and simplif...
2018-09-24 Florent Kermarrecsoc_core: add uart-stub argument
2018-09-19 Florent Kermarrectargets/sim: add ram-init param to allow initializing...
2018-09-19 Florent Kermarrecintegration/soc_core: add get_mem_data function to...
2018-09-08 enjoy-digitalMerge pull request #99 from cr1901/mk-copy-main-ram
2018-09-08 enjoy-digitalMerge pull request #100 from cr1901/tinyprog-fix
2018-09-05 Jean-François Nguyenadd Minerva support
2018-08-23 Tim AnsellMerge pull request #91 from cr1901/ignore-fix
2018-08-23 Tim AnsellMerge pull request #92 from cr1901/l2-gate
2018-08-21 Florent Kermarrecsoc_core: add cpu_endianness
2018-08-06 Florent Kermarrecsoc/integration/soc_core: add Controller with reset...
2018-07-17 enjoy-digitalMerge pull request #80 from xobs/fix-vexriscv-csr-read
2018-07-10 Florent Kermarrecsoc_core: add csr_expose parameter to be able to expose...
2018-07-05 Florent Kermarreccores/cpu/vexriscv: create variants: None and "debug...
2018-07-05 enjoy-digitalMerge pull request #77 from xobs/debug-vexriscv-enjoy
2018-07-05 Sean Crosssoc_core: uart: add a reset line to the UART
2018-07-05 Sean Crosssoc: integration: use the new cpu_debugging flag for...
2018-06-19 Florent Kermarrecsoc_core: remove assert on interrupt (added to catch...
2018-05-09 Dolu1990add VexRiscv support (imported/adapted from misoc)
2018-05-09 Florent Kermarrecallow multiple riscv32 softcores (use picorv32 cpu_type...
2018-04-30 Florent Kermarrecsoc/intergration/soc_core: don't delete uart/timer0...
2018-04-12 Florent Kermarrecsoc_core: uncomment uart interrupt deletion
2018-03-05 Florent Kermarrecsoc/integration/soc_core: improve error message for...
2018-03-05 enjoy-digitalMerge pull request #68 from mithro/improve-csr-missing...
2018-03-04 Tim 'mithro' AnsellImproving error message when csr name is not found.
2018-02-23 Florent Kermarrecreplace litex.gen imports with migen imports
2018-01-16 enjoy-digitalMerge pull request #51 from felixheld/liteeth-untangling
2018-01-13 Tim AnsellMerge pull request #49 from mithro/fix-uart-override
2018-01-13 Tim 'mithro' Ansellsoc_core: Don't fail if name is the same.
2017-12-30 Florent Kermarrecsoc/integration/soc_core: avoid removing uart interrupt...
2017-12-30 enjoy-digitalMerge pull request #40 from mithro/or1k-linux
2017-12-30 Tim 'mithro' Ansellcpu: Adding "variant" support.
2017-12-27 enjoy-digitalMerge pull request #38 from cr1901/mercury
2017-12-26 Florent Kermarrecsoc/integration/soc_core: add uart_name parameters...
2017-12-08 Florent Kermarrecsoc/integration/soc_core: add integrated_rom_init to...
2017-12-03 Florent Kermarrecsoc/integration/soc_core: make nmi interrupt optional
2017-11-24 Florent Kermarrecsoc/integration: add integrated_main_ram_init parameter...
2017-10-30 Tim AnsellMerge pull request #34 from mithro/uart-irq-change
2017-10-30 Tim 'mithro' AnsellMake the interrupt dicts read only.
2017-10-30 Tim 'mithro' AnsellMake it harder to have conflicting interrupts.
2017-10-30 Tim 'mithro' AnsellChange the default IRQs.
2017-09-26 enjoy-digitalMerge pull request #28 from enjoy-digital/eb-docs-2
2017-09-06 Florent Kermarrecsoc/integration/soc_core: add ident_version parameter...
2017-07-20 enjoy-digitalMerge pull request #26 from q3k/diamond-linux-support
2017-07-06 Florent Kermarrecsoc/core/uart: add UartStub to enable fast simulation...
2017-03-12 enjoy-digitalMerge pull request #22 from mithro/master
2017-03-12 Tim 'mithro' Ansellsoc_core: Add CPU_RESET_ADDR as a constant.
2017-01-30 Florent Kermarrecsoc/integration/soc_core: use cpu_reset_address = self...
2017-01-17 enjoy-digitalMerge pull request #14 from mithro/spiflash2
2017-01-14 enjoy-digitalMerge pull request #17 from mithro/master
2017-01-14 Tim 'mithro' AnsellFixing missing csr_constant/config support.
2017-01-13 Florent Kermarrecmerge most of misoc 54e1ef82 and migen e93d0601 changes
2016-12-17 enjoy-digitalMerge pull request #11 from mithro/file-dont-change
2016-12-17 enjoy-digitalMerge pull request #10 from mithro/etherbone
2016-12-17 Tim 'mithro' AnsellProvide csr_data_width via the constants.
2016-03-31 Florent Kermarrecinitial RISC-V support (with picorv32), still some...
2016-02-17 Florent Kermarrecsoc/integration/soc_core: instanciate wishbone/csr...
2016-01-14 Florent Kermarrecsoc/integration: return vns with soc and builder
2015-11-14 Florent Kermarrecsoc/interconnect/stream: add Cast and others small...
2015-11-14 Florent Kermarrecfix soc/integration/soc_core.py
2015-11-13 Florent Kermarrecfor now use our fork of migen (to be able to simulate...
2015-11-11 Florent Kermarrecsoc/integration/soc_core: add support for SoCs without CPU
2015-11-11 Florent Kermarrecavoid forking migen, we will add custom modules in...
2015-11-10 Florent Kermarrecsoc: merge with misoc 3fcc4f116c3292020cb811d179e45ae45...
2015-11-07 Florent Kermarreclitex: reorganize things, first work working version