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[litex.git] / litex / soc / interconnect / wishbone.py

2020-04-06	Florent Kermarrec	interconnect/csr, wishbone: use reset_less on datapath...	blob \| commitdiff \| raw
2020-02-24	Florent Kermarrec	litex_gen/wishbone: simplify the way the bus is exposed...	blob \| commitdiff \| raw \| diff to current
2020-02-24	enjoy-digital	Merge pull request #396 from antmicro/external-wb	blob \| commitdiff \| raw \| diff to current
2020-02-21	Jan Kowalewski	wishbone: add extracting module signals to the top	blob \| commitdiff \| raw \| diff to current
2020-02-08	enjoy-digital	Merge pull request #278 from scanakci/blackparrot_litex	blob \| commitdiff \| raw \| diff to current
2020-01-31	Florent Kermarrec	wishbone/Cache: add reverse parameter	blob \| commitdiff \| raw \| diff to current
2020-01-10	Florent Kermarrec	wishbone/Cache: avoid REFILL_WRTAG state to improve...	blob \| commitdiff \| raw \| diff to current
2019-11-20	enjoy-digital	Merge pull request #309 from antmicro/mmcm-fix	blob \| commitdiff \| raw \| diff to current
2019-10-11	Florent Kermarrec	interconnect/wishbone: fix Converter case when buses...	blob \| commitdiff \| raw \| diff to current
2019-10-11	Florent Kermarrec	soc_core: add automatic down-conversion of CPU buses...	blob \| commitdiff \| raw \| diff to current
2019-09-09	Florent Kermarrec	interconnect/wishbone: add FlipFlop to allow UpConverte...	blob \| commitdiff \| raw \| diff to current
2019-08-05	Florent Kermarrec	wishbone/SRAM: make read_only emited verilog code compa...	blob \| commitdiff \| raw \| diff to current
2019-06-23	Florent Kermarrec	add CONTRIBUTORS file and add copyright header to all...	blob \| commitdiff \| raw \| diff to current
2019-05-02	Florent Kermarrec	soc/interconnect/wishbone: allow setting adr_width...	blob \| commitdiff \| raw \| diff to current
2019-01-29	Florent Kermarrec	soc/integration/soc_core: allow disabling wishbone...	blob \| commitdiff \| raw \| diff to current
2019-01-27	Florent Kermarrec	soc/interconnect/wishbone: increase bus error timeout...	blob \| commitdiff \| raw \| diff to current
2018-11-26	enjoy-digital	Merge pull request #128 from mithro/small-fix	blob \| commitdiff \| raw \| diff to current
2018-11-25	Tim 'mithro' Ansell	wishbone.SRAM: Support non-32bit wishbone widths.	blob \| commitdiff \| raw \| diff to current
2018-08-06	Florent Kermarrec	soc/interconnect/wishbone: add Timeout to avoid stallin...	blob \| commitdiff \| raw \| diff to current
2018-02-23	Florent Kermarrec	replace litex.gen imports with migen imports	blob \| commitdiff \| raw \| diff to current
2017-01-17	enjoy-digital	Merge pull request #14 from mithro/spiflash2	blob \| commitdiff \| raw \| diff to current
2017-01-13	Florent Kermarrec	merge most of misoc 54e1ef82 and migen e93d0601 changes	blob \| commitdiff \| raw \| diff to current
2016-04-25	Florent Kermarrec	soc/interconnect/wishbone: add FlipFlop (should be...	blob \| commitdiff \| raw \| diff to current
2015-12-27	Florent Kermarrec	some cleanup	blob \| commitdiff \| raw \| diff to current
2015-11-13	Florent Kermarrec	for now use our fork of migen (to be able to simulate...	blob \| commitdiff \| raw \| diff to current
2015-11-11	Florent Kermarrec	avoid forking migen, we will add custom modules in...	blob \| commitdiff \| raw \| diff to current
2015-11-10	Florent Kermarrec	soc: merge with misoc 3fcc4f116c3292020cb811d179e45ae45...	blob \| commitdiff \| raw \| diff to current
2015-11-07	Florent Kermarrec	litex: reorganize things, first work working version	blob \| commitdiff \| raw \| diff to current

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