git.libre-soc.org Git - litex.git/history - litex/soc/interconnect/wishbone.py

2018-11-25	Tim 'mithro' Ansell	wishbone.SRAM: Support non-32bit wishbone widths.	blob \| commitdiff \| raw
2018-08-06	Florent Kermarrec	soc/interconnect/wishbone: add Timeout to avoid stallin...	blob \| commitdiff \| raw \| diff to current
2018-02-23	Florent Kermarrec	replace litex.gen imports with migen imports	blob \| commitdiff \| raw \| diff to current
2017-01-17	enjoy-digital	Merge pull request #14 from mithro/spiflash2	blob \| commitdiff \| raw \| diff to current
2017-01-13	Florent Kermarrec	merge most of misoc 54e1ef82 and migen e93d0601 changes	blob \| commitdiff \| raw \| diff to current
2016-04-25	Florent Kermarrec	soc/interconnect/wishbone: add FlipFlop (should be...	blob \| commitdiff \| raw \| diff to current
2015-12-27	Florent Kermarrec	some cleanup	blob \| commitdiff \| raw \| diff to current
2015-11-13	Florent Kermarrec	for now use our fork of migen (to be able to simulate...	blob \| commitdiff \| raw \| diff to current
2015-11-11	Florent Kermarrec	avoid forking migen, we will add custom modules in...	blob \| commitdiff \| raw \| diff to current
2015-11-10	Florent Kermarrec	soc: merge with misoc 3fcc4f116c3292020cb811d179e45ae45...	blob \| commitdiff \| raw \| diff to current
2015-11-07	Florent Kermarrec	litex: reorganize things, first work working version	blob \| commitdiff \| raw \| diff to current