soc/integration/cpu_interface: generate name for Memories in get_csr_header
[litex.git] / litex / soc / interconnect /
2018-12-16 Tim AnsellMerge pull request #135 from mithro/icestorm-ice40up5k
2018-12-08 Florent Kermarrecsoc/interconnect/stream: add support for buffered async...
2018-11-30 Florent Kermarrecsoc/interconnect/stream/gearbox: remove bit reversing...
2018-11-26 enjoy-digitalMerge pull request #128 from mithro/small-fix
2018-11-25 Tim 'mithro' Ansellstream.Endpoint: Pass extra arguments to superclass.
2018-11-25 Tim 'mithro' Ansellwishbone.SRAM: Support non-32bit wishbone widths.
2018-11-23 Florent Kermarrecsoc/interconnect/stream/gearbox: inverse bit order
2018-11-17 Florent Kermarrecsoc/interconnect/stream: add Gearbox
2018-10-30 Florent Kermarrecsoc/interconnect/stream_packet: use reverse_bytes from...
2018-08-06 Florent Kermarrecsoc/interconnect/wishbone: add Timeout to avoid stallin...
2018-07-17 enjoy-digitalMerge pull request #80 from xobs/fix-vexriscv-csr-read
2018-07-10 Florent Kermarrecsoc_core: add csr_expose parameter to be able to expose...
2018-02-23 Florent Kermarrecreplace litex.gen imports with migen imports
2018-02-21 enjoy-digitalMerge pull request #64 from q3k/q3k/axi4lite
2018-02-21 Sergiusz BazanskiChange AXI interface and tidy code
2018-02-20 Sergiusz BazanskiPreliminary AXI4Lite CSR bridge support
2017-11-23 Florent Kermarrecsoc/interconnect/stream: fix specific cases for last...
2017-10-30 Florent Kermarrecsoc/interconnect/stream: expose depth on SyncFIFO
2017-10-12 Florent Kermarrecsoc/interconnect/stream: don't use reset less on last...
2017-07-24 Florent Kermarrecsoc/interconnect/stream: fix make_m2s for reset_less
2017-06-30 Florent Kermarrecsoc/interconnect/wishbonebridge: reset_less optimizations
2017-06-30 Florent Kermarrecsoc/interconnect/stream_packet: reset_less optimizations
2017-06-30 Florent Kermarrecsoc/interconnect/stream: improve reset_less support...
2017-06-28 Florent Kermarrecsoc/interconnect/stream: use reset_less attr of signal...
2017-06-09 Florent Kermarrecsoc/interconnect/stream: add first signal to streams...
2017-03-28 Florent Kermarrecsoc/interconnect/stream_packet.py: make error payload...
2017-01-17 enjoy-digitalMerge pull request #14 from mithro/spiflash2
2017-01-13 Florent Kermarrecmerge most of misoc 54e1ef82 and migen e93d0601 changes
2017-01-10 Florent Kermarrecsoc/interconnect/stream/: add busy signal to PipelinedActor
2016-04-29 Florent Kermarrecmove sdram code to litedram (https://github.com/enjoy...
2016-04-25 Florent Kermarrecsoc/interconnect/wishbone: add FlipFlop (should be...
2016-04-21 Florent Kermarrecuse new Record.connect omit parameter (replace leave_out)
2016-04-15 Florent KermarrecMerge branch 'master' of https://github.com/enjoy-digit...
2016-04-13 Florent Kermarrecsoc/interconnect/dma_lasmi: change endpoint names
2016-04-12 Florent KermarrecMerge branch 'master' of https://github.com/enjoy-digit...
2016-04-07 Florent Kermarrecsoc/interconnect/stream/PipelinedActor: add latency...
2016-03-30 Florent Kermarrecsoc/interconnect/stream_sim: add more genericity to...
2016-03-23 Florent Kermarrecsoc/interconnect/stream_sim: use passive generators...
2016-03-21 Florent Kermarrecsoc/interconnect/stream_sim: adapt to new simulator
2016-03-16 Florent Kermarrecsoc/interconnect/stream: use valid/ready/last signals...
2016-03-16 Florent Kermarrecsoc/interconnect/wishbonebridge: fix import
2016-03-16 Florent Kermarrecsoc/interconnect/stream_packet: remove Buffer (we will...
2016-03-16 Florent Kermarrecsoc/interconnect/stream: remove busy signal, BufferizeE...
2016-03-16 Florent Kermarrecsoc: replace all Sink/Source with stream.Endpoint
2016-03-16 Florent Kermarrecsoc/interconnect/stream: use new Converter/StrideConverter
2016-03-16 Florent Kermarrecsoc/interconnect/stream: fix missing param
2016-03-16 Florent Kermarrecsoc/interconnect/stream: remove packetized parameter...
2016-03-15 Florent Kermarrecsoc/interconnect/stream: set packetized to True by...
2016-01-31 Florent Kermarrecsoc/interconnect/stream: fix merge issue (missing param...
2015-12-27 Florent Kermarrecsome cleanup
2015-12-19 Florent Kermarrecsoc/interconnect/stream: expose Endpoint
2015-11-28 Florent Kermarrecsoc/interconnect/stream: improve Pipeline to allow...
2015-11-27 Florent Kermarrecsoc/interconnect/stream_packet: add check of field...
2015-11-24 Florent Kermarrecsoc/interconnect/stream_packet: fix Counter removing
2015-11-17 Florent Kermarrecsoc/tools: initialize wishbone remote control (for...
2015-11-16 Florent Kermarrecsoc/interconnect/stream_packet: remove Counter
2015-11-16 Florent Kermarrecsoc/interconnect/wishbonebridge: remove Counter
2015-11-16 Florent Kermarrecsoc/interconnect/stream/SyncFIFO: expose fifo level
2015-11-14 Florent Kermarrecsoc/interconnect/stream: add Cast and others small...
2015-11-14 Florent Kermarrecadd TODOs
2015-11-13 Florent Kermarrecsoc/interconnect: add stream_sim
2015-11-13 Florent Kermarrecsoc/interconnect: rename packet to stream_packet
2015-11-13 Florent Kermarrecfor now use our fork of migen (to be able to simulate...
2015-11-12 Florent Kermarrecsoc/interconnect/stream: add BufferizeEndpoints
2015-11-12 Florent Kermarrecsoc/interconnect/stream: add Pipeline
2015-11-12 Florent Kermarrecsoc/interconnect/stream: reintroduce params
2015-11-11 Florent Kermarrecsoc/interconnect: add packet
2015-11-11 Florent Kermarrecsoc/interconnect: add wishbonebridge and uart bridge
2015-11-11 Florent Kermarrecsoc/interconnect/stream: reintroduce PipelinedActor...
2015-11-11 Florent Kermarrecavoid forking migen, we will add custom modules in...
2015-11-10 Florent Kermarrecsoc: merge with misoc 3fcc4f116c3292020cb811d179e45ae45...
2015-11-07 Florent Kermarreclitex: reorganize things, first work working version