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soc/integration/cpu_interface: generate name for Memories in get_csr_header
[litex.git] / litex / utils /
2019-01-03 Florent Kermarrecutils/litex_server: allow specify uart_baudrate as... tree | commitdiff
2018-12-27 Florent Kermarreclitex_sim: simplify, change sdram module and enable... tree | commitdiff
2018-11-27 Florent KermarrecMerge branch 'master' of github.com/enjoy-digital/litex tree | commitdiff
2018-11-27 enjoy-digitalMerge pull request #130 from jfng/master tree | commitdiff
2018-11-27 Jean-François Nguyenlitex_sim: add --trace argument tree | commitdiff
2018-11-26 enjoy-digitalMerge pull request #128 from mithro/small-fix tree | commitdiff
2018-11-22 Florent Kermarrecutils/litex_read_verilog: fix generated indent on instance tree | commitdiff
2018-11-16 Florent Kermarrecutils: add litex_read_verilog utility tree | commitdiff
2018-11-16 Florent Kermarreccreate utils directory and move the litex utils to it tree | commitdiff