soc/integration/cpu_interface: generate name for Memories in get_csr_header
[litex.git] / litex /
2019-01-05 Florent Kermarrecsoc/integration/cpu_interface: generate name for Memori...
2019-01-03 Florent Kermarrecutils/litex_server: allow specify uart_baudrate as...
2018-12-28 Florent Kermarrectargets/ulx3s: use pll for phase shift, enable refresh...
2018-12-28 Florent Kermarrectargets/versa_ecp5: use pll for phase shift, enable...
2018-12-28 Florent Kermarrecsoc/cores/clock/ECP5PLL: add basic phase support
2018-12-27 Florent Kermarreclitex_sim: simplify, change sdram module and enable...
2018-12-21 Florent Kermarrecbuild/sim/verilator: compile sim just before running...
2018-12-20 Tim AnsellMerge pull request #144 from mithro/nextpnr-migen-update
2018-12-20 Tim 'mithro' AnsellIntegrate latest migen changes for lattice/icestorm.
2018-12-20 Florent Kermarrecbuild/sim: handle verilog $finish and if coverage is...
2018-12-19 Florent Kermarrecplatforms/kcu105: change internal vref to 0.84v (recomm...
2018-12-19 Florent Kermarrecbios/sdram: only show read delays when they are valid.
2018-12-19 Florent Kermarrecbios/sdram: reduce write leveling scan range
2018-12-19 Florent Kermarrecsoc/cores/clock: remove return on S7PLL.create_clkout
2018-12-18 Florent Kermarrecplatforms/kcu105: set internal vref on ddr4 banks
2018-12-18 Florent Kermarrecupdate Ultrascale DDRPHY
2018-12-18 Tim AnsellMerge pull request #141 from mithro/xst-fix
2018-12-18 Tim 'mithro' AnsellFix `-vlgincdir` for xst.
2018-12-17 Florent Kermarrecbios/sdram: reduce scans verbosity on ultrascale
2018-12-17 Florent Kermarrecbios/sdram: use ddrphy_half_sys8x_taps_read() for KUSDDRPHY
2018-12-16 Tim AnsellMerge pull request #138 from mithro/mainram-hack
2018-12-16 Tim 'mithro' AnsellHack to fix #136.
2018-12-16 Tim AnsellMerge pull request #135 from mithro/icestorm-ice40up5k
2018-12-16 Tim 'mithro' AnsellAdd uwg30 package and up3k part.
2018-12-12 Florent Kermarrecsoc/cores/cpu/vexriscv: add add_debug method for debug...
2018-12-12 Florent Kermarrecsoc/cores/cpu/vexriscv: add support for the new variants.
2018-12-12 Florent Kermarrecsoc/cores/cpu/vexriscv: update submodule
2018-12-12 Florent Kermarrecsoc/cores/cpu/lm32: add submodule/rtl to include path...
2018-12-12 Florent Kermarrecbuild/sim/verilator: add support for plaform.sources...
2018-12-12 Florent Kermarrecbuild/microsemi/libero_soc: fix typos
2018-12-09 Florent Kermarrecgen/sim/core: add args support on Display
2018-12-09 Florent Kermarrecgen/fhdl: add simulation Display, Finish support.
2018-12-09 Florent Kermarrecbuild/sim: add coverage parameter to enable code coverage
2018-12-08 Florent Kermarrecsoc/interconnect/stream: add support for buffered async...
2018-12-04 Florent Kermarrecgen: integrate migen changes
2018-11-30 Florent Kermarrecsoc/interconnect/stream/gearbox: remove bit reversing...
2018-11-27 Florent KermarrecMerge branch 'master' of github.com/enjoy-digital/litex
2018-11-27 Florent Kermarrecbuild/xilinx/vivado: disable xpm by default (can be...
2018-11-27 enjoy-digitalMerge pull request #130 from jfng/master
2018-11-27 Florent Kermarrectargets/ulx3s, versa_ecp5: use ECP5PLL
2018-11-27 Jean-François Nguyenlitex_sim: add --trace argument
2018-11-27 Florent Kermarreccores/clock: test and fix ECP5PLL, phase still not...
2018-11-27 Florent Kermarrecboards/platforms/ulx3s: add gpios 0-3
2018-11-26 Florent Kermarrecbios/sdram: flush l2 cache only when present
2018-11-26 Florent Kermarrecbios: allow testing main_ram at init when using an...
2018-11-26 Florent Kermarrecbuild/microsemi/libero_soc: small cleanup
2018-11-26 enjoy-digitalMerge pull request #128 from mithro/small-fix
2018-11-25 Tim 'mithro' Ansellstream.Endpoint: Pass extra arguments to superclass.
2018-11-25 Tim 'mithro' Ansellwishbone.SRAM: Support non-32bit wishbone widths.
2018-11-23 Florent Kermarreccores/clock: add ECP5PLL
2018-11-23 Florent Kermarrecsoc/interconnect/stream/gearbox: inverse bit order
2018-11-23 Florent Kermarrecsoc/cores/spi_flash: add missing endianness parameter
2018-11-23 Florent Kermarrecplatforms/avalanche: add IOStandard on ddram pins
2018-11-23 Florent Kermarrecbuild/microsemi/libero_soc: associate timings constrain...
2018-11-23 Florent Kermarrecbuild/microsemi/libero_soc: add additional_timing_const...
2018-11-23 Florent Kermarrecbuild/microsemi/libero_soc: use die/package/speed from...
2018-11-23 Florent Kermarrecplatforms/avalanche: add package/speed to platform...
2018-11-23 Florent Kermarrecbuild/microsemi/libero_soc: remove previous impl direct...
2018-11-23 Florent Kermarrecbuild/microsemi/libero_soc: give better names to pdc...
2018-11-22 Florent Kermarrecbuild/microsemi/libero_soc: add additional_constraints
2018-11-22 Florent Kermarrecplatforms/avalanche: fix ddram dq7
2018-11-22 Florent Kermarrecbuild/microsemi/libero_soc: add {} around port name.
2018-11-22 Florent Kermarrecutils/litex_read_verilog: fix generated indent on instance
2018-11-21 Florent Kermarrecsoc/integration/soc_core: add csr_map_update function
2018-11-21 Tim AnsellMerge pull request #127 from cr1901/picorv32-data
2018-11-21 William D. Joneslibbase/crt0-picorv32: Add support for .data sections.
2018-11-20 Florent Kermarrecbuild/sim/verilator: add trace parameter to enable...
2018-11-20 Florent Kermarrecsoc_core: convert cpu_type="None" string to None
2018-11-19 Florent Kermarrecbuild/microsemi/libero_soc: only associate timings...
2018-11-19 Florent Kermarrecbuild/microsemi/common: add async reset synchronizer...
2018-11-19 Florent Kermarrecbuild/microsemi/libero_soc: pass timing constraints...
2018-11-19 Florent Kermarrecbuild/microsemi/libero_soc: add timing constraints...
2018-11-19 Florent Kermarrecboards/platforms/avalanche: fix swapped serial pins
2018-11-19 Florent Kermarrecboards/platforms/avalanche: rename rst to rst_n (active...
2018-11-19 Florent Kermarrecbuild/microsemi/libero_soc: associate .pdc to place...
2018-11-17 Florent Kermarrecsoc/interconnect/stream: add Gearbox
2018-11-16 Florent Kermarrecutils: add litex_read_verilog utility
2018-11-16 Florent Kermarreccreate utils directory and move the litex utils to it
2018-11-16 Florent Kermarrecbuild/microsemi/libero_soc: able to generate design...
2018-11-15 Florent Kermarrecbuild: add microsemi template for polarfire fpgas support
2018-11-14 Tim AnsellMerge pull request #126 from mithro/toolchain-fix
2018-11-14 Tim 'mithro' Anselllattice/icestorm: Add toolchain_path so it doesn't...
2018-11-13 Florent Kermarrecsoc_core: check for cpu before checking interrupt
2018-11-13 Florent Kermarreccores/clock/S7: just reset the generated clock, not...
2018-11-13 Florent Kermarrecbios/main: fix typo on mor1kx
2018-11-13 Florent Kermarreccpu/mor1kx: use clang only for linux variant
2018-11-12 Florent Kermarrecxilinx/vivado: fix migen merge
2018-11-12 Florent Kermarrecplatforms: remove versaecp55g_sdram
2018-11-12 Florent Kermarrecbuild/xilinx/vivado: merge migen change
2018-11-12 Florent Kermarrecbuild: use default toolchain_path on all backend when...
2018-11-12 Florent Kermarrecgeneric_platform: use set for sources
2018-11-12 Florent Kermarrecbuild: merge more migen changes
2018-11-12 Florent Kermarrecplatforms/versa_ecp5: import migen changes
2018-11-12 Florent Kermarrectargets/ulx3s,versa_ecp5: prjtrellis toolchain renamed...
2018-11-12 Florent Kermarrecbuild/lattice: import changes from migen
2018-11-12 Florent Kermarrectargets/versa_ecp5: increase sys_clk_freq to 50MHz
2018-11-12 Florent Kermarrectargets: add versa_ecp5 with sdram (ecp5 soc hat) at...
2018-11-12 Florent Kermarrectargets/ulx3s: for now revert to 25MHz clock/no pll
2018-11-12 Florent Kermarrecplatforms/versa_ecp5: add ecp5 soc hat ios
2018-11-12 Florent KermarrecMerge branch 'master' of github.com/enjoy-digital/litex
next