mibuild/lattice/diamond: add verilog include path (thanks Lattice's FAE since it...
[litex.git] / mibuild / generic_platform.py
2015-03-18 Florent Kermarrecfhdl/verilog: revert "fhdl/verilog: add simulation...
2015-03-16 Florent Kermarrecfhdl/verilog: add simulation parameter to avoid simulat...
2015-03-13 Sebastien Bourdeauducqmibuild: sanitize default clock management
2015-03-13 Sebastien Bourdeauducqmibuild: get rid of Platform factory function, cleanup
2015-02-18 Yann Sionneaumibuild: support pin names in IO extensions
2015-02-14 Sebastien Bourdeauducqmibuild: make resolve_signals public
2015-02-14 Florent Kermarrecmibuild: return verilog namespace with build
2014-10-17 Florent Kermarrecremove trailing whitespaces
2014-08-02 Florent Kermarrecmibuild/generic_platform: add recursive parameter to...
2014-07-09 Fabien Marteaumibuild/generic_platform.py: adding ability to use...
2014-02-17 Sebastien Bourdeauducqmibuild/generic_platform: fix default value for connectors
2014-02-16 Sebastien Bourdeauducqmibuild: support for expansion connectors
2013-12-12 Sebastien Bourdeauducqadd support for Verilog include paths
2013-12-01 Sebastien Bourdeauducqmibuild: use keyword arguments directly in build_cmdline
2013-11-23 Sebastien Bourdeauducqmerge Mibuild into Migen
2013-11-23 Sebastien BourdeauducqAdd 'mibuild/' from commit '9d5931c969810a236de2a2713cf...
2013-08-12 Nina Engelhardtadd mist synthesis mode to build
2013-08-03 Nina Engelhardtadd edif build routines
2013-07-26 Sebastien BourdeauducqFragment -> _Fragment
2013-07-04 Sebastien BourdeauducqCall finalize() after CRG creation
2013-06-27 Robert Jordens* generic_platform.py: add a finalize() method
2013-06-25 Sebastien BourdeauducqShorter multipin signal definition
2013-05-26 Sebastien BourdeauducqUse migen.fhdl.std
2013-03-26 Sebastien BourdeauducqSupport for platform info
2013-03-26 Sebastien Bourdeauducqgeneric_platform: remove obj in request + add lookup_re...
2013-03-18 Sebastien Bourdeauducqgeneric_platform: do not create clock domains during...
2013-03-15 Sebastien BourdeauducqNew clock_domain API
2013-03-12 Sebastien Bourdeauducqgeneric_platform: implicit get_fragment
2013-02-23 Sebastien Bourdeauducqgeneric_platform/get_verilog: pass additional args...
2013-02-23 Sebastien Bourdeauducqcorelogic -> genlib
2013-02-20 Sebastien Bourdeauducqgeneric_platform: prefix subsignals
2013-02-14 Sebastien Bourdeauducqgeneric_platform: add name
2013-02-13 Sebastien Bourdeauducqgeneric_platform: fix IO signal set when using existing...
2013-02-12 Sebastien Bourdeauducqgeneric_platform: get absolute path for added sources
2013-02-11 Sebastien Bourdeauducqgeneric_platform: fix request
2013-02-08 Sebastien BourdeauducqSupport for command line arguments
2013-02-08 Sebastien BourdeauducqSupport adding Verilog/VHDL files
2013-02-08 Sebastien Bourdeauducqgeneric_platform: support name remapping
2013-02-08 Sebastien Bourdeauducqgeneric_platform: fix typo
2013-02-07 Sebastien BourdeauducqInitial version