import migen in litex/gen
[litex.git] / migen / fhdl / verilog.py
2015-11-07 Florent KermarrecMerge remote-tracking branch 'migen/master'
2015-11-05 Sebastien Bourdeauducqfhdl/verilog: create clock domains in deterministic...
2015-11-04 Sebastien BourdeauducqMerge 'new' branch
2015-10-19 Sebastien Bourdeauducqverilog, sim: accept iterables in FHDL statements
2015-09-26 Sebastien Bourdeauducqfhdl: replace flen with len
2015-09-22 Sebastien Bourdeauducqfhdl/namer: support ClockSignal and ResetSignal. Closes #24
2015-09-21 Sebastien Bourdeauducqverilog: remove unneeded import
2015-09-17 Sebastien Bourdeauducqfhdl/verilog: fix case value sort
2015-09-15 Sebastien Bourdeauducqfhdl/structure: introduce Constant, autowrap for eq...
2015-09-11 Sebastien Bourdeauducqstyle
2015-05-23 Florent Kermarrecfhdl/verilog: add reserved keywords
2015-04-24 Florent Kermarrecmigen/fhdl/verilog: _printheader/_printcomb, remove...
2015-04-24 Florent Kermarrecmigen/fhdl: give explicit names to syntax specializatio...
2015-04-21 Guy Hutchisonfhdl/verilog: add flag to produce ASIC-friendly output
2015-04-13 Florent Kermarrecrevert fhdl/verilog: avoid reg initialization in printh...
2015-04-13 Florent Kermarrecglobal: pep8 (E302)
2015-04-13 Florent Kermarrecglobal: pep8 (replace tabs with spaces)
2015-04-13 Florent KermarrecMerge branch 'master' of https://github.com/m-labs...
2015-04-10 Florent Kermarrecfhdl/verilog: avoid reg initialization in printheader...
2015-04-08 Sebastien Bourdeauducqintroduce conversion output object (prevents file IO...
2015-03-30 Sebastien BourdeauducqRevert "migen: create VerilogConvert and EDIFConvert...
2015-03-30 Sebastien BourdeauducqRevert "migen/fhdl: pass fdict filename --> contents...
2015-03-30 Sebastien BourdeauducqRevert "migen/fhdl/specials: use fdict to pass memory...
2015-03-30 Florent Kermarrecmigen/fhdl/specials: use fdict to pass memory initializ...
2015-03-30 Florent Kermarrecmigen/fhdl: pass fdict filename --> contents to specials
2015-03-30 Florent Kermarrecmigen: create VerilogConvert and EDIFConvert classes...
2015-03-18 Sebastien Bourdeauducqfhdl/verilog: fix dummy signal initial event
2015-03-18 Florent Kermarrecfhdl/verilog: change the way we initialize reg: reg...
2015-03-18 Florent Kermarrecfhdl/verilog: revert "fhdl/verilog: add simulation...
2015-03-18 Sebastien BourdeauducqRevert "fhdl/verilog: do not use initial begin in _prin...
2015-03-16 Florent Kermarrecfhdl/verilog: add simulation parameter to avoid simulat...
2015-03-16 Florent Kermarrecfhdl/verilog: do not use initial begin in _printinit...
2014-11-01 Sebastien BourdeauducqMerge branch 'master' of github.com:m-labs/migen
2014-10-29 Sebastien Bourdeauducqfhdl/verilog: fix tristate to instance connection
2014-10-17 Florent Kermarrecremove trailing whitespaces
2013-12-11 Sebastien Bourdeauducqfhdl/verilog: fix representation of negative integers
2013-12-03 Robert Jordensfhdl.size: rename to bitcontainer
2013-11-23 Sebastien BourdeauducqAdd 'mibuild/' from commit '9d5931c969810a236de2a2713cf...
2013-08-12 Nina Engelhardtadd ternary operator sel ? a : b
2013-08-08 Sebastien Bourdeauducqfhdl: move insert_resets to tools
2013-07-26 Nina Engelhardtfix synthesis translate on/off switch
2013-07-25 Sebastien Bourdeauducqfhdl: do not export Fragment
2013-06-30 Sebastien Bourdeauducqfhdl/verilog: lower complex slices before reset insertion
2013-06-26 Sebastien Bourdeauducqfhdl/verilog: fix signedness rules for comparison
2013-06-24 Sebastien Bourdeauducqfhdl/verilog: improve error reporting
2013-05-22 Sebastien BourdeauducqNew migen.fhdl.std to simplify imports + len->flen
2013-04-25 Sebastien Bourdeauducqfhdl/verilog: recursive Special lowering
2013-04-23 Florent KermarrecSupport for resetless clock domains
2013-04-11 Sebastien Bourdeauducqfhdl/verilog/_printinit: initialize undriven Special...
2013-03-26 Sebastien Bourdeauducqfhdl/specials: clean up clock domain handling
2013-03-18 Sebastien Bourdeauducqfhdl/verilog: optionally disable clock domain creation
2013-03-18 Sebastien BourdeauducqLowering of Special expressions + support ClockSignal...
2013-03-17 Sébastien BourdeauducqMerge pull request #6 from larsclausen/master
2013-03-15 Sebastien BourdeauducqMake ClockDomains part of fragments
2013-03-12 Sebastien Bourdeauducqfhdl/verilog: implicit get_fragment
2013-03-06 Sebastien Bourdeauducqfhdl/verilog: tristate outputs are always wire
2013-02-27 Sebastien Bourdeauducqfhdl/verilog: insert reset before listing signals
2013-02-23 Sebastien Bourdeauducqfhdl/verilog: support special lowering and overrides
2013-02-22 Sebastien BourdeauducqNew 'specials' API
2013-02-14 Sebastien Bourdeauducqfhdl: tristate support
2013-01-23 Sebastien Bourdeauducqfhdl/verilog: fix spurious clock/reset signals on multi...
2013-01-05 Sebastien Bourdeauducqfhdl: support nested statement lists
2012-11-29 Sebastien BourdeauducqFix various errors from new bitwidth/signedness system...
2012-11-29 Sebastien Bourdeauducqfhdl/verilog: make signal behave as integers in arithme...
2012-11-29 Sebastien BourdeauducqNew specification for width and signedness
2012-11-29 Sebastien BourdeauducqRefactor Case
2012-11-28 Sebastien BourdeauducqRemove Constant
2012-11-23 Sebastien Bourdeauducqfhdl: use object creation counter (HUID) as hash. This...
2012-11-18 Sebastien Bourdeauducqfhdl/verilog: remove empty cases
2012-09-22 Sebastien Bourdeauducqfhdl: support expressions in instance ports
2012-09-22 Sebastien Bourdeauducqfhdl: support inverted clock ports in instances
2012-09-11 Sebastien Bourdeauducqfhdl/verilog: sort clock domains by name
2012-09-11 Sebastien Bourdeauducqfhdl: list signals in execution order
2012-09-10 Sebastien BourdeauducqMerge branch 'master' of github.com:milkymist/migen
2012-09-10 Sebastien BourdeauducqMulti-clock design support + new instance API
2012-09-09 Sébastien BourdeauducqMerge pull request #3 from brandonhamilton/upstream
2012-07-13 Sebastien Bourdeauducqx.bv.width -> len(x)
2012-07-13 Sebastien Bourdeauducqfhdl: remove _StatementList
2012-07-09 Sebastien Bourdeauducqfhdl: arrays (TODO: use correct BV for intermediate...
2012-04-30 Sebastien Bourdeauducqfhdl/verilog: add option to display which comb blocks...
2012-04-02 Sebastien Bourdeauducqfhdl: phase out pads
2012-04-02 Sebastien Bourdeauducqfhdl/verilog: do not attempt to initialize instance...
2012-04-01 Sebastien Bourdeauducqfhdl/verilog: initialize internal read-only signals...
2012-03-06 Sebastien Bourdeauducqfhdl/verilog: fix signed constant conversion
2012-02-17 Sebastien Bourdeauducqfhdl/verilog: properly connect instance inouts
2012-02-16 Sebastien Bourdeauducqfhdl: support forwarding of bidirectional signals from...
2012-02-06 Sebastien Bourdeauducqfhdl: do not attempt slicing non-array signals to keep...
2012-01-27 Sebastien Bourdeauducqfhdl: memories working
2012-01-27 Sebastien Bourdeauducqfhdl/verilog: clean up signal classification and suppor...
2012-01-20 Sebastien BourdeauducqInclude fragment pads in pre-naming dictionary
2012-01-20 Sebastien BourdeauducqFix instance support
2012-01-20 Sebastien BourdeauducqInclude unused I/Os in pre-naming dictionary and regist...
2012-01-19 Sebastien BourdeauducqNew naming system: second attempt
2012-01-16 Sebastien BourdeauducqNew naming system beginning to work
2012-01-16 Sebastien Bourdeauducqfhdl: new naming system (broken)
2012-01-15 Sebastien Bourdeauducqfhdl: allow None statements
2012-01-07 Sebastien Bourdeauducqverilog: split comb block, use assign statements
2012-01-06 Sebastien Bourdeauducqconvtools -> tools
2012-01-05 Sebastien BourdeauducqMerge branch 'master' of github.com:milkymist/migen
2012-01-05 Sebastien BourdeauducqConvert -> convert
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