framebuffer: fake DMA for testing (WIP)
[litex.git] / milkymist /
2012-07-01 Sebastien Bourdeauducqframebuffer: fake DMA for testing (WIP)
2012-07-01 Sebastien Bourdeauducqframebuffer/vtg: fix dataflow control (inc. WA for...
2012-07-01 Sebastien Bourdeauducqframebuffer: fix pixel split
2012-07-01 Sebastien Bourdeauducqframebuffer: fix sync generation
2012-07-01 Sebastien Bourdeauducqframebuffer: register output of FIFO
2012-07-01 Sebastien Bourdeauducqframebuffer: video timing generator
2012-07-01 Sebastien Bourdeauducqframebuffer: FIFO
2012-06-29 Sebastien Bourdeauducqframebuffer: VTG and FIFO skeleton
2012-06-29 Sebastien Bourdeauducqframebuffer: chop memory words
2012-06-24 Sebastien Bourdeauducqframebuffer: ala flow->actorlib
2012-06-22 Sebastien Bourdeauducqframebuffer: control.For -> misc.IntSequence
2012-06-17 Sebastien Bourdeauducqframebuffer: address generator and DMA
2012-06-17 Sebastien Bourdeauducqframebuffer: frame initiator
2012-06-17 Sebastien BourdeauducqVGA framebuffer connections
2012-05-22 Sebastien BourdeauducqClock frequency detection
2012-05-21 Sebastien Bourdeauducqminimac: add tx start register
2012-05-21 Sebastien BourdeauducqAdd timer
2012-05-19 Sebastien BourdeauducqAdd Ethernet MAC
2012-05-16 Sebastien BourdeauducqIdentifier
2012-05-15 Sebastien Bourdeauducqasmicon/multiplexer: fix read tag delay
2012-04-02 Sebastien BourdeauducqRemove uses of pads, new constraints system
2012-04-01 Sebastien Bourdeauducqasmicon: various fixes. Now produces convincing refresh...
2012-03-31 Sebastien Bourdeauducqasmicon/bankmachine: fixes
2012-03-30 Sebastien Bourdeauducqasmicon/refresher: fix refresh sequence done signal
2012-03-18 Sebastien Bourdeauducqasmicon: multiplexer (untested)
2012-03-18 Sebastien Bourdeauducqasmicon: move slot time to timing settings
2012-03-17 Sebastien Bourdeauducqasmicon: bank machine (untested)
2012-03-15 Sebastien Bourdeauducqasmicon: refresher (untested)
2012-03-15 Sebastien Bourdeauducqnorflash: use new timeline API
2012-03-14 Sebastien Bourdeauducqasmicon: skeleton
2012-02-24 Sebastien Bourdeauducqddrphy: request wrdata_en/rddata_en at the same time...
2012-02-23 Sebastien Bourdeauducqdfii: set data mask
2012-02-23 Sebastien Bourdeauducqdfii: new design
2012-02-20 Sebastien Bourdeauducqs6ddrphy: write path OK in simulation
2012-02-19 Sebastien BourdeauducqPrepare for new DDR PHY
2012-02-18 Sebastien BourdeauducqSend SDRAM initialization sequence and answer PHY read...
2012-02-17 Sebastien BourdeauducqDFI injector (untested)
2012-02-17 Sebastien BourdeauducqMap DDR PHY controls in CSR
2012-02-17 Sebastien BourdeauducqConnect DDR PHY
2012-02-16 Sebastien Bourdeauducqclkfx: remove
2012-02-16 Sebastien Bourdeauducqm1crg: make clock feedback pin bidirectional
2012-02-16 Sebastien Bourdeauducqlm32: compatibility with the new instance API
2012-02-16 Sebastien BourdeauducqGenerate all clocks for the DDR PHY
2012-02-15 Sebastien BourdeauducqUse new bus API
2012-02-07 Sebastien Bourdeauducquart: RX support
2012-02-06 Sebastien Bourdeauducqsram: fix sub-word write
2012-02-06 Sebastien BourdeauducqUART: use new bank API and event manager
2012-02-03 Sebastien Bourdeauducqsram: fix WE signal
2012-01-27 Sebastien BourdeauducqRemove explicit bus names
2012-01-27 Sebastien BourdeauducqAdd on-chip SRAM
2012-01-21 Sebastien BourdeauducqUse meaningful class names
2012-01-13 Sebastien BourdeauducqWishbone: omit fixed LSBs
2012-01-05 Sebastien BourdeauducqConvert -> convert
2011-12-18 Sebastien BourdeauducqUse new syntax
2011-12-17 Sebastien Bourdeauducquart: new design using FHDL and bank (TX only, incomplete)
2011-12-17 Sebastien Bourdeauducq32-device, 8-bit CSR bus
2011-12-17 Sebastien Bourdeauducqclkfx module
2011-12-16 Sebastien BourdeauducqProper reset generation
2011-12-16 Sebastien BourdeauducqSupport the new FHDL syntax
2011-12-16 Sebastien BourdeauducqPay a bit more attention to PEP8
2011-12-13 Sebastien BourdeauducqInitial import