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bug #1183: attempt first ddffirst mapreduce mode
[openpower-isa.git]
/
openpower
/
isa
/
bitmanip.mdwn
2023-12-22
Luke Kenneth Casso...
add first gather instruction pseudocode
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2023-12-22
Jacob Lifshay
remove grev, leaving unit tests for later use by grevlut
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2023-06-02
Luke Kenneth Casso...
https://bugs.libre-soc.org/show_bug.cgi?id=1091
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2023-06-02
Jacob Lifshay
add shaddw
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2023-06-02
Jacob Lifshay
spelling fix
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2023-06-02
Dmitry Selyutin
bitmanip.mdwn: add missing Rc static operand
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2023-06-02
Dmitry Selyutin
bitmanip.mdwn: avoid overflow for m variable
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2023-06-02
Dmitry Selyutin
Revert "Revert "https://bugs.libre-soc.org/show_bug...
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2023-06-02
Dmitry Selyutin
Revert "corrections to shadd/uw after reverting to...
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2023-06-02
Luke Kenneth Casso...
corrections to shadd/uw after reverting to switch
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2023-06-02
Luke Kenneth Casso...
Revert "https://bugs.libre-soc.org/show_bug.cgi?id...
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2023-06-02
Luke Kenneth Casso...
https://bugs.libre-soc.org/show_bug.cgi?id=966#c4
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2023-06-02
Luke Kenneth Casso...
comments
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2023-06-02
Luke Kenneth Casso...
shadd pseudocode cleanup
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2023-06-02
Dmitry Selyutin
bitmanip.mdwn: support shadd/shadduw instructions
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2022-08-30
Luke Kenneth Casso...
correct the bitmanip pseudocode to remove spaces from...
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2022-05-03
Jacob Lifshay
add Rc to ternlogi
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2022-01-18
Jacob Lifshay
grev[w][i][.] pseudo-code works
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2022-01-14
Jacob Lifshay
remove stray newline
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2022-01-14
Jacob Lifshay
add grev[w][i][.] pseudo-code
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2021-12-11
Luke Kenneth Casso...
remove ROTL64(1, idx), just use TLI[7-idx] it is shorte...
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2021-12-11
Luke Kenneth Casso...
use concat in ternlogi to reduce code size
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2021-12-10
Jacob Lifshay
change ternlogi to not have Rc field
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2021-12-09
Jacob Lifshay
add initial ternlogi pseudo-code
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