convert basic_pypowersim to hex rather than broken octal (?)
[openpower-isa.git] / openpower / isa /
2023-12-22 Jacob Lifshayremove grev, leaving unit tests for later use by grevlut
2023-12-22 Jacob Lifshaydemo moving pseudocode to separate file
2023-12-22 Jacob Lifshayfix set[n]bc[r]
2023-12-22 Jacob Lifshayadd set[n]bc[r] -- tests broken
2023-12-22 Jacob Lifshayadd pdepd/pextd
2023-12-22 Jacob Lifshayadd cfuged
2023-12-22 Jacob Lifshayadd cntlzdm/cnttzdm
2023-12-22 Konstantinos Marga... Moved maddsubrs/maddrs/msubrs instructions to separate...
2023-12-22 Konstantinos Marga... Fix failing cases, all tests pass now
2023-12-22 Jacob Lifshayadd byte reverse instructions from PowerISA v3.1B
2023-12-22 Konstantinos Marga... Unify XLEN =64 special case in the new code
2023-12-22 Konstantinos Marga... Fix XLEN != 64 cases where maddsubrs fails
2023-12-22 Jacob Lifshayadd fminmax tests with corresponding pseudocode fixes
2023-12-22 Jacob Lifshayupdate to use new fminmax instruction
2023-12-22 Jacob Lifshayrename fmv[ft]g*/fcvt[ft]g* to m[tf]fpr*/c[tf]fpr*
2023-12-22 Jacob Lifshayremove Rc=1 from fmvfg[s]
2023-12-22 Jacob Lifshayremove fcvttgs since it's redundant
2023-06-02 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=1091
2023-06-02 Jacob Lifshayfcvttg[s][o][.] needs EXTRA_UNINIT_REGS: RT
2023-06-02 Jacob Lifshayfix: bfp_ROUND_TO_BFP64 takes 3 arguments
2023-06-02 Jacob Lifshayfix fcvttg FPSCR.FR computation
2023-06-02 Jacob Lifshayfix bug in fcvttg OpenPower and saturating conversion
2023-06-02 Jacob Lifshayrephrase to avoid personal pronouns
2023-06-02 Jacob Lifshayduplicate overflow comment as requested by luke
2023-06-02 Jacob Lifshayfix fcvttg* overflow/FPSCR computation
2023-06-02 Jacob Lifshayfix bugs in fcvt* pseudocode
2023-06-02 Jacob Lifshayundefined is a function that needs to be called
2023-06-02 Jacob Lifshayswitch fpcvt over to using FPSCR attributes
2023-06-02 Konstantinos Marga... merge maddrs/msubrs, unit tests changed accordingly
2023-06-02 Konstantinos Marga... Add 2 more instructions to help with 2-coeff butterfly
2023-06-02 Konstantinos Marga... use a simpler way to do the same thing
2023-06-02 Konstantinos Marga... Handle large 64-bit values, but only the low 64-bit...
2023-06-02 Konstantinos Marga... do proper rounding, no rounding for SH=0 (for now)...
2023-06-02 Konstantinos Marga... Result needs rounding so add +1 to prod*
2023-06-02 Konstantinos Marga... handle negatives correctly by adding sign bit to final...
2023-06-02 Konstantinos Marga... almost there, positive values work, negative values...
2023-06-02 Konstantinos Marga... use proper register sizes
2023-06-02 Konstantinos Marga... MULS instead of MUL, RA instead of RT in in1
2023-06-02 Konstantinos Marga... Turns out DCTI-Form is another variant of A-Form
2023-06-02 Konstantinos Marga... minor fixes in pseudocode, CONST_UI->CONST_SH in minor_...
2023-06-02 Konstantinos Marga... WIP: maddsubrs initial approach
2023-06-02 Jacob Lifshayadd fcvt/fmv -- no tests yet
2023-06-02 Jacob Lifshaycomment fmin*/fmax* since they're being replaced with...
2023-06-02 Luke Kenneth Casso... ffnmadds converted to 3-operand
2023-06-02 Luke Kenneth Casso... converted ffnmadds to 3-operand
2023-06-02 Luke Kenneth Casso... ffmsubs number of operands reduced to match ffmadds
2023-06-02 Luke Kenneth Casso... reduce number of operands to ffmadds as well
2023-06-02 Jacob Lifshayprefix-sum remap works!
2023-06-02 Luke Kenneth Casso... reduce fdmadds down to only 3 operands, RT-overwrite...
2023-06-02 Luke Kenneth Casso... add SVSHAPE setup for parallel/prefix but it refuses...
2023-06-02 Jacob Lifshayreplace min/max[su][.] with minmax[.]
2023-06-02 Jacob Lifshayrewrite all uses of XLCASTU/XLCASTS
2023-06-02 Jacob Lifshayuse proper cast function
2023-06-02 Jacob Lifshaychange XLEN-ification
2023-06-02 Jacob Lifshaychange extsb/h/w to scale based on XLEN rather than...
2023-06-02 Jacob Lifshayadd shaddw
2023-06-02 Jacob Lifshayspelling fix
2023-06-02 Luke Kenneth Casso... remove DCT/iDCT redundant modes which require less...
2023-06-02 Luke Kenneth Casso... update comments on svstep returning pack/unpack state
2023-06-02 Luke Kenneth Casso... updated simplev setvl specification pseudocode: MAJOR...
2023-06-02 Luke Kenneth Casso... update pseudocode for dsld/dsrd to note that only when...
2023-06-02 Dmitry Selyutinbitmanip.mdwn: add missing Rc static operand
2023-06-02 Jacob Lifshayadd maddedus
2023-06-02 Jacob LifshayXLEN-ify maddedu
2023-06-02 Jacob Lifshayfix maddedu title line
2023-06-02 Dmitry Selyutinbitmanip.mdwn: avoid overflow for m variable
2023-06-02 Dmitry SelyutinRevert "Revert "https://bugs.libre-soc.org/show_bug...
2023-06-02 Dmitry SelyutinRevert "corrections to shadd/uw after reverting to...
2023-06-02 Luke Kenneth Casso... corrections to shadd/uw after reverting to switch
2023-06-02 Luke Kenneth Casso... Revert "https://bugs.libre-soc.org/show_bug.cgi?id...
2023-06-02 Luke Kenneth Casso... dsld: MASK(0, 63-n) works just as well as MASK(64,...
2023-06-02 Luke Kenneth Casso... overflow condition in dsld and dsrd if RS is non-zero
2023-06-02 Luke Kenneth Casso... fix dsrd pseudocode to use ROTL64 not ROTL128
2023-06-02 Luke Kenneth Casso... fix dsld pseudocode to use ROTL64 instead of ROTL128
2023-06-02 Luke Kenneth Casso... fix dsrd, ROTL128 use 128-n not 64-n,
2023-06-02 Luke Kenneth Casso... fix dsrd pseudocode for new 3-in 2-out
2023-06-02 Luke Kenneth Casso... sort out dsld pseudocode, creating mask is tricky
2023-06-02 Luke Kenneth Casso... endeavouring to implement shift-carry-dsld
2023-06-02 Luke Kenneth Casso... first cut pseudocode for dsld/dsrd to be 3-in 1-out,
2023-06-02 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=966#c4
2023-06-02 Luke Kenneth Casso... code-comments on divmod2du and maddedu are wrong
2023-06-02 Luke Kenneth Casso... comments
2023-06-02 Luke Kenneth Casso... shadd pseudocode cleanup
2023-06-02 Dmitry Selyutinbitmanip.mdwn: support shadd/shadduw instructions
2023-06-02 Luke Kenneth Casso... add maxs. combined with cmp capability
2023-06-02 Luke Kenneth Casso... argh, extremely annoying: 4-operand dsld/dsrd is not...
2023-06-02 Luke Kenneth Casso... bigint shuffle
2023-06-02 Luke Kenneth Casso... use XLEN/2 for ROTL32 in fixedshift.mdwn
2023-06-02 Luke Kenneth Casso... add first chacha20 round test
2023-06-02 Dmitry Selyutinav.mdwn: fix missing bmask operand
2023-06-02 Dmitry Selyutinav.mdwn: fix Rc-augmented cprop instruction
2023-06-02 Luke Kenneth Casso... whoops missed an update MEM(EA...) in pifixedstore
2022-10-11 Luke Kenneth Casso... whoops ea not ra in pifixedstore.mdwn
2022-10-11 Luke Kenneth Casso... add sv.stwu/pi example in test_sv_load_store_postinc
2022-10-11 Luke Kenneth Casso... add Post-increment version of fixedstore.mdwn
2022-10-11 Luke Kenneth Casso... add experimental post-increment fixedload pseudocode
2022-10-10 Luke Kenneth Casso... add elwidth overrides on Indexed REMAP, 8-bit example...
2022-10-08 Luke Kenneth Casso... misnamed instruction, lfiwzx
2022-10-01 Luke Kenneth Casso... remove special case from setvl calling SVSTATE_NEXT,
2022-10-01 Jacob Lifshayincrease pcdec. output compression by skipping impossib...
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