compute CR1 for non-compare fp Rc=1 instructions
[openpower-isa.git] / openpower /
2023-06-02 Jacob Lifshayfix fcvttg FPSCR.FR computation
2023-06-02 Jacob Lifshayadd fmv*/fcvt* to sv_analysis.py
2023-06-02 Jacob Lifshayfix bug in fcvttg OpenPower and saturating conversion
2023-06-02 Jacob Lifshayadd more fp -> int bfp* functions
2023-06-02 Jacob Lifshayfix fp comparison
2023-06-02 Jacob Lifshayfix round nearest-even
2023-06-02 Jacob Lifshayadd bfp_CONVERT_FROM_UI32/64
2023-06-02 Jacob Lifshayrephrase to avoid personal pronouns
2023-06-02 Jacob Lifshayduplicate overflow comment as requested by luke
2023-06-02 Jacob Lifshayfix fcvttg* overflow/FPSCR computation
2023-06-02 Jacob Lifshayfix mis-computed exponent in bfp_CONVERT_FROM_BFP64
2023-06-02 Luke Kenneth Casso... fix sv_analysis ldux, missing s/d:RA
2023-06-02 Luke Kenneth Casso... some empty slots now in RM and also source=dest in...
2023-06-02 Luke Kenneth Casso... ld/st mismatch in power_insn.py and sv_analysis.py
2023-06-02 Luke Kenneth Casso... in DCT/FFT 3-in 2-out set had to make RT same source...
2023-06-02 Luke Kenneth Casso... classify LD/ST-Immediate-Update as EXTRA3.
2023-06-02 Jacob Lifshayadd rest of bfp_* helpers needed to run fcvt js test
2023-06-02 Jacob Lifshayfix `even` polarity in bfp_ROUND_TO_INTEGER
2023-06-02 Jacob Lifshayfix bugs in fcvt* pseudocode
2023-06-02 Jacob Lifshayadd some bfp_* functions -- this isn't yet enough to...
2023-06-02 Jacob Lifshayundefined is a function that needs to be called
2023-06-02 Jacob Lifshayswitch to using self.FPSCR
2023-06-02 Jacob Lifshayswitch to using FPSCRState for double2single.mdwn
2023-06-02 Jacob Lifshayswitch fpcvt over to using FPSCR attributes
2023-06-02 Dmitry Selyutinminor_19.csv: convert RA to RA0 for minmax
2023-06-02 Jacob Lifshayadd initial fmv/fcvt tests, though they're broken due...
2023-06-02 Jacob Lifshayverify fields.txt forms' field separators ('|') line...
2023-06-02 Konstantinos Marga... merge maddrs/msubrs, unit tests changed accordingly
2023-06-02 Konstantinos Marga... Add 2 more instructions to help with 2-coeff butterfly
2023-06-02 Konstantinos Marga... use a simpler way to do the same thing
2023-06-02 Konstantinos Marga... Handle large 64-bit values, but only the low 64-bit...
2023-06-02 Konstantinos Marga... do proper rounding, no rounding for SH=0 (for now)...
2023-06-02 Konstantinos Marga... Result needs rounding so add +1 to prod*
2023-06-02 Konstantinos Marga... handle negatives correctly by adding sign bit to final...
2023-06-02 Konstantinos Marga... almost there, positive values work, negative values...
2023-06-02 Konstantinos Marga... use proper register sizes
2023-06-02 Konstantinos Marga... MULS instead of MUL, RA instead of RT in in1
2023-06-02 Konstantinos Marga... Turns out DCTI-Form is another variant of A-Form
2023-06-02 Konstantinos Marga... minor fixes in pseudocode, CONST_UI->CONST_SH in minor_...
2023-06-02 Konstantinos Marga... WIP: maddsubrs initial approach
2023-06-02 Jacob Lifshayfix forgotten stuff from last commit
2023-06-02 Jacob Lifshayadd fcvt/fmv -- no tests yet
2023-06-02 Jacob Lifshayadd all fmv*/fcvt* fields
2023-06-02 Jacob Lifshaysplit XO-Form's RA field in prep for adding fcvttg...
2023-06-02 Jacob Lifshaycomment fmin*/fmax* since they're being replaced with...
2023-06-02 Jacob Lifshayupdate SV csvs
2023-06-02 Luke Kenneth Casso... ffnmadds converted to 3-operand
2023-06-02 Luke Kenneth Casso... converted ffnmadds to 3-operand
2023-06-02 Luke Kenneth Casso... ffmsubs number of operands reduced to match ffmadds
2023-06-02 Luke Kenneth Casso... reduce number of operands to ffmadds as well
2023-06-02 Jacob Lifshayprefix-sum remap works!
2023-06-02 Luke Kenneth Casso... reduce fdmadds down to only 3 operands, RT-overwrite...
2023-06-02 Luke Kenneth Casso... add SVSHAPE setup for parallel/prefix but it refuses...
2023-06-02 Luke Kenneth Casso... add CW and CW2 Form
2023-06-02 Jacob Lifshayreplace min/max[su][.] with minmax[.]
2023-06-02 Jacob Lifshayadd unofficial and comment2 columns to minor_19.csv
2023-06-02 Jacob Lifshayadd MM-form
2023-06-02 Jacob Lifshayrewrite all uses of XLCASTU/XLCASTS
2023-06-02 Jacob Lifshayuse proper cast function
2023-06-02 Jacob Lifshaychange XLEN-ification
2023-06-02 Jacob Lifshaychange extsb/h/w to scale based on XLEN rather than...
2023-06-02 Jacob Lifshayadd shaddw
2023-06-02 Jacob Lifshayspelling fix
2023-06-02 Jacob Lifshayfix `neg[o].` causing the simulator to raise TypeError
2023-06-02 Luke Kenneth Casso... remove DCT/iDCT redundant modes which require less...
2023-06-02 Luke Kenneth Casso... update comments on svstep returning pack/unpack state
2023-06-02 Luke Kenneth Casso... updated simplev setvl specification pseudocode: MAJOR...
2023-06-02 Luke Kenneth Casso... whoops added "CRB-Form" format not "CRB"
2023-06-02 Luke Kenneth Casso... add CRB-Form fields for crternlogi and crbinlog, they...
2023-06-02 Luke Kenneth Casso... update pseudocode for dsld/dsrd to note that only when...
2023-06-02 Dmitry Selyutinfields.text: fix TLI XO format
2023-06-02 Dmitry Selyutinbitmanip.mdwn: add missing Rc static operand
2023-06-02 Dmitry Selyutinisatables: split dsld/dsrd Rc versions
2023-06-02 Dmitry Selyutinpower_insn: support tables priorities
2023-06-02 Jacob Lifshayadd maddedus
2023-06-02 Jacob LifshayXLEN-ify maddedu
2023-06-02 Jacob Lifshayfix maddedu title line
2023-06-02 Dmitry Selyutinbitmanip.mdwn: avoid overflow for m variable
2023-06-02 Dmitry SelyutinRevert "Revert "https://bugs.libre-soc.org/show_bug...
2023-06-02 Dmitry SelyutinRevert "corrections to shadd/uw after reverting to...
2023-06-02 Luke Kenneth Casso... corrections to shadd/uw after reverting to switch
2023-06-02 Luke Kenneth Casso... Revert "https://bugs.libre-soc.org/show_bug.cgi?id...
2023-06-02 Luke Kenneth Casso... dsld: MASK(0, 63-n) works just as well as MASK(64,...
2023-06-02 Luke Kenneth Casso... overflow condition in dsld and dsrd if RS is non-zero
2023-06-02 Luke Kenneth Casso... fix dsrd pseudocode to use ROTL64 not ROTL128
2023-06-02 Luke Kenneth Casso... fix dsld pseudocode to use ROTL64 instead of ROTL128
2023-06-02 Jacob Lifshayupdate csvs to match make output
2023-06-02 Luke Kenneth Casso... fix dsrd, ROTL128 use 128-n not 64-n,
2023-06-02 Luke Kenneth Casso... redo sv_analysis for dsld/dsrd
2023-06-02 Luke Kenneth Casso... fix dsrd pseudocode for new 3-in 2-out
2023-06-02 Luke Kenneth Casso... sort out dsld pseudocode, creating mask is tricky
2023-06-02 Luke Kenneth Casso... endeavouring to implement shift-carry-dsld
2023-06-02 Luke Kenneth Casso... redo the 3-in 1-out move of dsld/dsrd to EXT04 VA2...
2023-06-02 Luke Kenneth Casso... first cut pseudocode for dsld/dsrd to be 3-in 1-out,
2023-06-02 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=966#c4
2023-06-02 Luke Kenneth Casso... code-comments on divmod2du and maddedu are wrong
2023-06-02 Luke Kenneth Casso... comments
2023-06-02 Luke Kenneth Casso... shadd pseudocode cleanup
2023-06-02 Dmitry Selyutinbitmanip.mdwn: support shadd/shadduw instructions
2023-06-02 Dmitry Selyutinminor_4.csv: support shadd/shadduw instructions
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