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[openpower-isa.git] / openpower /
2021-08-15 Luke Kenneth Casso... sv.bc test jumping to wrong location (offset 0xc not...
2021-08-14 Luke Kenneth Casso... end loop condition in svp64 bc pseudo-code
2021-08-11 Luke Kenneth Casso... corrections to SVP64 Branch Conditional
2021-08-08 Luke Kenneth Casso... add bc and bclr to sv_analysis
2021-08-07 Luke Kenneth Casso... remove SVP64 Branch format modifications (achieve a...
2021-08-05 Luke Kenneth Casso... add SVP64 Branch-Conditional equivalent of Rc fields
2021-08-02 Luke Kenneth Casso... add inverse DCT in-place unit test with bit-reversed...
2021-08-01 Luke Kenneth Casso... bit of a big update, remove all bit-reversed LD operati...
2021-08-01 Luke Kenneth Casso... add BCD operations to SVP64
2021-08-01 Luke Kenneth Casso... rename lw*br to lw*sh
2021-08-01 Luke Kenneth Casso... add LD-half-swap for i-DCT which does not work. redesig...
2021-07-31 Dmitry Selyutinisa/bcd: DPD_TO_BCD helper
2021-07-31 Dmitry Selyutinisa/bcd: BCD_TO_DPD helper
2021-07-31 Luke Kenneth Casso... replace DOUBLE function from helpers.py with pseudocode...
2021-07-31 Luke Kenneth Casso... add SINGLE function to double2single, to replace manual...
2021-07-31 Luke Kenneth Casso... add outer-inner RADIX2 iDCT unit test.
2021-07-31 Dmitry Selyutinisa/bcd.mdwn: fix incorrect declaration
2021-07-31 Luke Kenneth Casso... add SVP64 i-DCT unit test for inner butterfly, coeffici...
2021-07-31 Luke Kenneth Casso... add i-DCT SVP64 unit test for outer butterfly
2021-07-31 Luke Kenneth Casso... add iDCT modes to interim svshape instruction pseudo...
2021-07-30 Dmitry Selyutinisa/bcd.mdwn: fix assignment operator
2021-07-30 Dmitry Selyutinisa/bcd.mdwn: update addg6s pseudocode
2021-07-30 Dmitry Selyutinisatables: cbcdtd instruction
2021-07-30 Dmitry Selyutinisatables: cdtbcd instruction
2021-07-28 Luke Kenneth Casso... argh, have LD-bitreverse select the offset from RA...
2021-07-28 Luke Kenneth Casso... add mode for half-swap, to be combined with LD-bit...
2021-07-27 Luke Kenneth Casso... get DCT shortened table operational
2021-07-27 Dmitry Selyutinisatables: addg6s instruction
2021-07-27 Luke Kenneth Casso... adding reduced COS table DCT test
2021-07-27 Luke Kenneth Casso... add new DCT inner butterfly shorter COS-gen mode unit...
2021-07-27 Luke Kenneth Casso... fix up DCT modes for inner/outer butterfly,
2021-07-27 Luke Kenneth Casso... fix errors in detection of ffmadds (etc), enabling...
2021-07-27 Luke Kenneth Casso... clear persist bit if setvl explicitly called
2021-07-27 Luke Kenneth Casso... add new cos coefficient pre-computed and on-the-fly...
2021-07-26 Luke Kenneth Casso... use ydimsz as sub-mode in DCT/FFT butterfly
2021-07-24 Luke Kenneth Casso... added an extra SVP64 instruction, svstep, to replace...
2021-07-24 Luke Kenneth Casso... add ability to get current SVSHAPE indices into a register,
2021-07-24 Luke Kenneth Casso... comments
2021-07-24 Luke Kenneth Casso... make REMAP persistent (if persistence requested) even...
2021-07-24 Luke Kenneth Casso... create schedule for calculating COS coefficient in DCT
2021-07-23 Luke Kenneth Casso... add DCT outer butterfly iterative overlapping ADD schedule
2021-07-23 Luke Kenneth Casso... add DCT outer butterfly svshape setup
2021-07-23 Luke Kenneth Casso... small inner DCT butterfly test, fix up order of fdmadds
2021-07-23 Luke Kenneth Casso... "fix" fdmadd DCT mul-add-sub unit test with values...
2021-07-23 Luke Kenneth Casso... add sv.fdmadds unit test
2021-07-23 Luke Kenneth Casso... add DCT mul-add to CSV and enums
2021-07-23 Luke Kenneth Casso... add DCT variant of twin MUL-ADD. actually an add and...
2021-07-23 Luke Kenneth Casso... add DCT butterfly mode into svremap
2021-07-20 Luke Kenneth Casso... realised that SVSHAPE0-3 is not privileged
2021-07-19 Luke Kenneth Casso... bit of a reorg, adding option to test end of inner...
2021-07-17 Luke Kenneth Casso... add FP LOAD bit-reversed operations to ISACaller simulator
2021-07-16 Luke Kenneth Casso... add fsins and fcoss to simulator
2021-07-15 Luke Kenneth Casso... stop using MSR vfirst bit, move to SVSTATE bit 63 instead
2021-07-15 Luke Kenneth Casso... add extra "persistence" bit to svremap instruction
2021-07-15 Luke Kenneth Casso... big intrusive update: merge SVREMAP with SVSTATE, remov...
2021-07-14 Luke Kenneth Casso... update SVSTATE to 64 bit length
2021-07-11 Luke Kenneth Casso... minor reordering of setvl and svshape: svshape is now...
2021-07-11 Luke Kenneth Casso... update svremap instruction to correctly store immediate...
2021-07-11 Luke Kenneth Casso... whoops 0b00002 is not binary
2021-07-11 Luke Kenneth Casso... add SVREMAP new Form / Fields and CSV entry
2021-07-11 Luke Kenneth Casso... add SVREMAP SPR
2021-07-11 Luke Kenneth Casso... rename svremap to svshape
2021-07-11 Luke Kenneth Casso... rename svremap to svshape
2021-07-10 Luke Kenneth Casso... add sv.ffadds unit test, inversion of subtract needed...
2021-07-10 Luke Kenneth Casso... add ffadds decoding:
2021-07-10 Luke Kenneth Casso... corrections to remaining fft madd/msub
2021-07-08 Luke Kenneth Casso... add ability to explicitly increment SVSTATE srcstep...
2021-07-08 Luke Kenneth Casso... add in extra "vertical" mode into SVP64 setvl
2021-07-07 Luke Kenneth Casso... get butterfly RADIX2 SVP64 example working, breaks...
2021-07-06 Luke Kenneth Casso... add FFT REMAP butterfly unit test
2021-07-06 Luke Kenneth Casso... add FFT SHAPE pseudocode in svremap, and a schedule...
2021-07-05 Luke Kenneth Casso... fix svremap field offsets
2021-07-05 Luke Kenneth Casso... add svremap manual instruction (Primary Opcode 22,...
2021-07-02 Luke Kenneth Casso... add basic README for media tests
2021-07-01 Luke Kenneth Casso... add temporary SV pseudocode
2021-07-01 Luke Kenneth Casso... add TEMPORARY svremap form and instruction
2021-06-28 Luke Kenneth Casso... add extra offset for FRB, for FFT Cooley-Tukey twin...
2021-06-27 Luke Kenneth Casso... add new (experimental) ffmadds and ffmsubs, for FFT...
2021-06-27 Luke Kenneth Casso... change name to OP_FP_MADD to identify fmadd (etc)
2021-06-27 Luke Kenneth Casso... add SVP64 FFT mode to PowerDecoder, add CSV entries
2021-06-26 Luke Kenneth Casso... use If Elif in power_decoder conditions, a lot easier...
2021-06-26 Luke Kenneth Casso... rename bit-reversed LDs to match v3.0B (strip "br")
2021-06-25 Luke Kenneth Casso... identify SVP64 LD bit-reverse pattern as pseudo-assembler
2021-06-25 Luke Kenneth Casso... update sv_analysis.py to match new CONDITIONs field...
2021-06-25 Luke Kenneth Casso... rename svp64 bit-reversed LD instructions to not confli...
2021-06-24 Luke Kenneth Casso... whoops SVP64 bit-rev LDs need to use SVD and SVDS immed...
2021-06-24 Luke Kenneth Casso... add major.csv LD operations with SVP64BREV condition
2021-06-24 Luke Kenneth Casso... add extra CONDITION column to CSVs
2021-06-23 Luke Kenneth Casso... only add SVP64 bitreverse mode for LDs at the moment...
2021-06-23 Luke Kenneth Casso... add SVP64 LD/ST "bitrev" alternative CSV
2021-06-23 Luke Kenneth Casso... add sv bitrev "major" CSV table
2021-06-23 Luke Kenneth Casso... looks like spec error on maddhd etc. should be a comma...
2021-06-23 Luke Kenneth Casso... add comments for SVP64 FP FFT/DCT
2021-06-23 Luke Kenneth Casso... add FFT/DCT to titles
2021-06-23 Luke Kenneth Casso... add SV FP arithmetic in "Overflow" mode for FFT/DCT +/-
2021-06-23 Luke Kenneth Casso... use SHL64 function for shift because "<<" operator...
2021-06-23 Luke Kenneth Casso... add in bitreverse function call into svfixedload
2021-06-23 Luke Kenneth Casso... add RC and SVD/SVDS-Form to svfixedload
2021-06-23 Luke Kenneth Casso... add svfixedload.mdwn at correct place
2021-06-23 Luke Kenneth Casso... add SVD-Form and SVDS-Form, variants of fixedload for...
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