sigh, bm not mode argument to bmask
[openpower-isa.git] / openpower /
2022-06-24 Luke Kenneth Casso... sigh, bm not mode argument to bmask
2022-06-24 Luke Kenneth Casso... add to fields.txt for the svstep instruction
2022-06-24 Luke Kenneth Casso... add svindex SVI-Form to fields.txt
2022-06-24 Jacob Lifshayadd missed generated csv changes
2022-06-23 Luke Kenneth Casso... add BM2-Form to power_enums.py
2022-06-23 Luke Kenneth Casso... else must be on separate line in pseudocode av.mdwn
2022-06-23 Luke Kenneth Casso... missing "Special Registers Altered" on av.mdwn
2022-06-23 Andrey MiroshnikovAdded bmask, pywriter failing
2022-06-23 Luke Kenneth Casso... add SPDX-License-Headers to CSV files
2022-06-23 Luke Kenneth Casso... add explanatory comments on minor_22.csv
2022-06-23 Luke Kenneth Casso... add comment-stripping to get_csv()
2022-06-22 Luke Kenneth Casso... add BM2 Form for (DRAFT) bmask instruction
2022-06-22 Andrey MiroshnikovModified cprop pseudo-code due to parser bug
2022-06-22 Andrey MiroshnikovAdded entries for cprop, not sure if correct
2022-06-20 Luke Kenneth Casso... add absolute-signed-diff next to absolute-unsigned...
2022-06-20 Luke Kenneth Casso... rename absadd[us] to absdac[ud]
2022-06-19 Jacob Lifshayfix minu[.] to be unsigned
2022-06-19 Luke Kenneth Casso... add absadds - signed accumulating add. DRAFT
2022-06-19 Luke Kenneth Casso... add absadd (unsigned) DRAFT
2022-06-19 Luke Kenneth Casso... add absolute-difference DRAFT
2022-06-19 Luke Kenneth Casso... add average-add DRAFT pseudocode and CSV
2022-06-19 Luke Kenneth Casso... add the rest of min/max DRAFT av opcodes
2022-06-19 Luke Kenneth Casso... add maxs DRAFT instruction
2022-06-19 Luke Kenneth Casso... extend minor_22.csv bitsel pattern to cover bits 21..31
2022-06-17 Luke Kenneth Casso... add KAIVB SPR 850
2022-05-20 Luke Kenneth Casso... bit of a mess being sorted out
2022-05-19 Dmitry Selyutintemporarily revert opcode changes
2022-05-19 Dmitry Selyutinisatables/minor_22.csv: reflect a new XO bit
2022-05-18 Luke Kenneth Casso... add BM-Form and CRB-Form for bitmanip
2022-05-16 Luke Kenneth Casso... add to VA-Form, alter XO on SVM and SVRM Form
2022-05-16 Luke Kenneth Casso... add VA2-Form for Bitmanip ops [DRAFT]
2022-05-15 Luke Kenneth Casso... add L field to TLI-Form for grwvlut
2022-05-14 Luke Kenneth Casso... cut/paste error resulted in Rc=0 twice, should be Rc=1
2022-05-14 Luke Kenneth Casso... cut/paste error resulted in Rc=0 twice, should be Rc=1
2022-05-12 Luke Kenneth Casso... add "DRAFT" in front of svfparith instruction descriptions
2022-05-03 Luke Kenneth Casso... code-comments on madded and divmod2du should say RS...
2022-05-03 Luke Kenneth Casso... properly fix pagereader.py to parse markdown with inden...
2022-05-03 Jacob Lifshayadd Rc to ternlogi
2022-05-03 Jacob Lifshayfix syntax error
2022-05-02 Luke Kenneth Casso... re-run sv_analysis to add mode field to csvs
2022-04-29 Luke Kenneth Casso... higher bits need to be checked for overflow not lower
2022-04-29 Luke Kenneth Casso... invert RC and RA, making divmod2du more like divdu
2022-04-27 Luke Kenneth Casso... accidentally added svfixedarith.mdwn to wiki rather...
2022-01-18 Jacob Lifshaygrev[w][i][.] pseudo-code works
2022-01-14 Jacob Lifshayremove stray newline
2022-01-14 Jacob Lifshayadd grev[w][i][.] pseudo-code
2022-01-06 Jacob Lifshayadd grev[w][i] instructions
2022-01-06 Luke Kenneth Casso... add tlbsync and wait as NOPs
2022-01-05 Luke Kenneth Casso... add eieio instruction as a NOP to minor 31 csv
2021-12-11 Luke Kenneth Casso... remove ROTL64(1, idx), just use TLI[7-idx] it is shorte...
2021-12-11 Luke Kenneth Casso... use concat in ternlogi to reduce code size
2021-12-10 Jacob Lifshaychange ternlogi to not have Rc field
2021-12-10 Jacob Lifshayadd .gitignore to ignore the generated vhdl
2021-12-09 Jacob Lifshayadd initial ternlogi pseudo-code
2021-12-02 Jacob Lifshaymove ternlogi to SHIFT_ROT unit
2021-11-17 Jacob Lifshayrename ternary->ternlog and associated form/field TI...
2021-11-13 Jacob Lifshayremove excess I from ternary-related names
2021-11-12 Jacob Lifshaychange ternaryi to correct register fields
2021-11-05 Jacob Lifshayadd ternaryi
2021-11-05 Jacob Lifshayadd comment2 and unofficial fields to existing instructions
2021-11-04 Tobias Platendcbz needs to go through ldst function unit
2021-10-13 Dmitry Selyutinfixedlogical: simplify extsw
2021-10-13 Dmitry Selyutinfixedlogical: simplify extsh
2021-10-13 Dmitry Selyutinfixedlogical: simplify extsb
2021-10-10 Luke Kenneth Casso... corrections to EXTSXL 0x000000090000093 table for extsb...
2021-10-10 Dmitry Selyutinisafunctions/extsxl: fix one of markdown tables
2021-10-04 Luke Kenneth Casso... corrections to csv files
2021-10-04 Luke Kenneth Casso... add another extsxl csv file
2021-10-04 Luke Kenneth Casso... replace f with F in csv files
2021-10-04 Luke Kenneth Casso... add extsxl csv files
2021-10-04 Luke Kenneth Casso... test adding extsxl data
2021-10-04 Luke Kenneth Casso... add blank example file
2021-09-29 Dmitry Selyutinfixedlogical: switch xoris to XCASTU
2021-09-29 Dmitry Selyutinfixedlogical: switch oris to XCASTU
2021-09-29 Dmitry Selyutinfixedlogical: switch andis. to XCASTU
2021-09-29 Dmitry Selyutinfixedlogical: switch xori to XCASTU
2021-09-29 Dmitry Selyutinfixedlogical: switch ori to XCASTU
2021-09-29 Dmitry Selyutinfixedlogical: switch andi. to XLCASTU
2021-09-07 Dmitry Selyutinfixedtrap: switch tw to XLEN
2021-09-07 Dmitry Selyutinfixedtrap: switch twi to XLEN
2021-09-07 Jacob LifshayXLEN-ify bcd instructions
2021-09-04 Dmitry Selyutincomparefixed: switch cmpeqb to XLEN
2021-09-04 Dmitry Selyutincomparefixed: switch cmprb to XLEN
2021-09-04 Dmitry Selyutincomparefixed: switch cmpl to XLEN
2021-09-04 Dmitry Selyutincomparefixed: switch cmpli to XLEN
2021-09-04 Dmitry Selyutincomparefixed: switch cmp to XLEN
2021-09-04 Dmitry Selyutincomparefixed: switch cmpi to XLEN
2021-09-03 Dmitry Selyutinfixedstore: switch stwux to XLEN
2021-09-03 Dmitry Selyutinfixedstore: switch stwu to XLEN
2021-09-03 Dmitry Selyutinfixedstore: switch stwx to XLEN
2021-09-03 Dmitry Selyutinfixedstore: switch stw to XLEN
2021-09-03 Dmitry Selyutinfixedstore: switch sthux to XLEN
2021-09-03 Dmitry Selyutinfixedstore: switch sthu to XLEN
2021-09-03 Dmitry Selyutinfixedstore: switch sthx to XLEN
2021-09-03 Dmitry Selyutinfixedstore: switch sth to XLEN
2021-09-03 Dmitry Selyutinfixedstore: switch stbux to XLEN
2021-09-03 Dmitry Selyutinfixedstore: switch stbu to XLEN
2021-09-03 Dmitry Selyutinfixedstore: switch stbx to XLEN
2021-09-03 Dmitry Selyutinfixedstore: switch stb to XLEN
2021-09-03 Luke Kenneth Casso... use brackets round (XLEN/2) in divw pseudocode
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