fixedload: switch lhz to XLEN
[openpower-isa.git] / openpower /
2021-08-31 Dmitry Selyutinfixedload: switch lhz to XLEN
2021-08-31 Dmitry Selyutinfixedload: switch lhzx to XLEN
2021-08-31 Dmitry Selyutinfixedload: switch lhzu to XLEN
2021-08-31 Dmitry Selyutinfixedload: switch lhzux to XLEN
2021-08-31 Dmitry Selyutinfixedlogical: switch cnttzd to XLEN
2021-08-30 Dmitry Selyutinfixedlogical: bpermd fixup
2021-08-30 Dmitry Selyutinfixedlogical: switch popcntw to XLEN
2021-08-30 Dmitry Selyutinfixedarith: switch modud to XLEN
2021-08-30 Dmitry Selyutinfixedarith: switch divdeuX to XLEN
2021-08-30 Dmitry Selyutinfixedarith: switch moduw to XLEN
2021-08-30 Dmitry Selyutinfixedarith: switch divwuX to XLEN
2021-08-30 Dmitry Selyutinfixedarith: switch divduX to XLEN
2021-08-30 Dmitry Selyutinfixedarith: switch maddhd to XLEN
2021-08-30 Dmitry Selyutinfixedarith: switch maddld to XLEN
2021-08-30 Dmitry Selyutinfixedarith: switch maddhdu to XLEN
2021-08-30 Dmitry Selyutinfixedarith: switch mulli to XLEN
2021-08-30 Dmitry Selyutinfixedarith: switch mulhdu to XLEN
2021-08-30 Dmitry Selyutinfixedarith: switch mulhd to XLEN
2021-08-30 Dmitry Selyutinfixedarith: switch mulldX to XLEN
2021-08-30 Dmitry Selyutinfixedarith: switch mulhwu to XLEN
2021-08-30 Dmitry Selyutinfixedarith: switch mullwX to XLEN
2021-08-30 Dmitry Selyutinfixedarith: switch mulhw to XLEN
2021-08-30 Dmitry Selyutinfixedlogical: switch bpermd to XLEN
2021-08-30 Dmitry Selyutinfixedlogical: switch cntlzd to XLEN
2021-08-30 Dmitry Selyutinfixedlogical: switch popcntd to XLEN
2021-08-30 Dmitry Selyutinfixedlogical: switch extsw to XLEN
2021-08-30 Dmitry Selyutinfixedlogical: switch prtyw to XLEN
2021-08-30 Dmitry Selyutinfixedlogical: switch prtyd to XLEN
2021-08-30 Dmitry Selyutinfixedlogical: switch popcntb to XLEN
2021-08-30 Dmitry Selyutinfixedlogical: switch cmpb to XLEN
2021-08-30 Dmitry Selyutinfixedlogical: switch cntlzwX to XLEN
2021-08-30 Dmitry Selyutinfixedlogical: switch xori to XLEN
2021-08-30 Dmitry Selyutinfixedlogical: switch xoris to XLEN
2021-08-30 Dmitry Selyutinfixedlogical: switch oris to XLEN
2021-08-30 Dmitry Selyutinfixedlogical: switch andis. to XLEN
2021-08-30 Dmitry Selyutinfixedlogical: switch ori to XLEN
2021-08-30 Dmitry Selyutinfixedlogical: switch andi. to XLEN
2021-08-15 Luke Kenneth Casso... sv.bc test jumping to wrong location (offset 0xc not...
2021-08-14 Luke Kenneth Casso... end loop condition in svp64 bc pseudo-code
2021-08-11 Luke Kenneth Casso... corrections to SVP64 Branch Conditional
2021-08-08 Luke Kenneth Casso... add bc and bclr to sv_analysis
2021-08-07 Luke Kenneth Casso... remove SVP64 Branch format modifications (achieve a...
2021-08-05 Luke Kenneth Casso... add SVP64 Branch-Conditional equivalent of Rc fields
2021-08-02 Luke Kenneth Casso... add inverse DCT in-place unit test with bit-reversed...
2021-08-01 Luke Kenneth Casso... bit of a big update, remove all bit-reversed LD operati...
2021-08-01 Luke Kenneth Casso... add BCD operations to SVP64
2021-08-01 Luke Kenneth Casso... rename lw*br to lw*sh
2021-08-01 Luke Kenneth Casso... add LD-half-swap for i-DCT which does not work. redesig...
2021-07-31 Dmitry Selyutinisa/bcd: DPD_TO_BCD helper
2021-07-31 Dmitry Selyutinisa/bcd: BCD_TO_DPD helper
2021-07-31 Luke Kenneth Casso... replace DOUBLE function from helpers.py with pseudocode...
2021-07-31 Luke Kenneth Casso... add SINGLE function to double2single, to replace manual...
2021-07-31 Luke Kenneth Casso... add outer-inner RADIX2 iDCT unit test.
2021-07-31 Dmitry Selyutinisa/bcd.mdwn: fix incorrect declaration
2021-07-31 Luke Kenneth Casso... add SVP64 i-DCT unit test for inner butterfly, coeffici...
2021-07-31 Luke Kenneth Casso... add i-DCT SVP64 unit test for outer butterfly
2021-07-31 Luke Kenneth Casso... add iDCT modes to interim svshape instruction pseudo...
2021-07-30 Dmitry Selyutinisa/bcd.mdwn: fix assignment operator
2021-07-30 Dmitry Selyutinisa/bcd.mdwn: update addg6s pseudocode
2021-07-30 Dmitry Selyutinisatables: cbcdtd instruction
2021-07-30 Dmitry Selyutinisatables: cdtbcd instruction
2021-07-28 Luke Kenneth Casso... argh, have LD-bitreverse select the offset from RA...
2021-07-28 Luke Kenneth Casso... add mode for half-swap, to be combined with LD-bit...
2021-07-27 Luke Kenneth Casso... get DCT shortened table operational
2021-07-27 Dmitry Selyutinisatables: addg6s instruction
2021-07-27 Luke Kenneth Casso... adding reduced COS table DCT test
2021-07-27 Luke Kenneth Casso... add new DCT inner butterfly shorter COS-gen mode unit...
2021-07-27 Luke Kenneth Casso... fix up DCT modes for inner/outer butterfly,
2021-07-27 Luke Kenneth Casso... fix errors in detection of ffmadds (etc), enabling...
2021-07-27 Luke Kenneth Casso... clear persist bit if setvl explicitly called
2021-07-27 Luke Kenneth Casso... add new cos coefficient pre-computed and on-the-fly...
2021-07-26 Luke Kenneth Casso... use ydimsz as sub-mode in DCT/FFT butterfly
2021-07-24 Luke Kenneth Casso... added an extra SVP64 instruction, svstep, to replace...
2021-07-24 Luke Kenneth Casso... add ability to get current SVSHAPE indices into a register,
2021-07-24 Luke Kenneth Casso... comments
2021-07-24 Luke Kenneth Casso... make REMAP persistent (if persistence requested) even...
2021-07-24 Luke Kenneth Casso... create schedule for calculating COS coefficient in DCT
2021-07-23 Luke Kenneth Casso... add DCT outer butterfly iterative overlapping ADD schedule
2021-07-23 Luke Kenneth Casso... add DCT outer butterfly svshape setup
2021-07-23 Luke Kenneth Casso... small inner DCT butterfly test, fix up order of fdmadds
2021-07-23 Luke Kenneth Casso... "fix" fdmadd DCT mul-add-sub unit test with values...
2021-07-23 Luke Kenneth Casso... add sv.fdmadds unit test
2021-07-23 Luke Kenneth Casso... add DCT mul-add to CSV and enums
2021-07-23 Luke Kenneth Casso... add DCT variant of twin MUL-ADD. actually an add and...
2021-07-23 Luke Kenneth Casso... add DCT butterfly mode into svremap
2021-07-20 Luke Kenneth Casso... realised that SVSHAPE0-3 is not privileged
2021-07-19 Luke Kenneth Casso... bit of a reorg, adding option to test end of inner...
2021-07-17 Luke Kenneth Casso... add FP LOAD bit-reversed operations to ISACaller simulator
2021-07-16 Luke Kenneth Casso... add fsins and fcoss to simulator
2021-07-15 Luke Kenneth Casso... stop using MSR vfirst bit, move to SVSTATE bit 63 instead
2021-07-15 Luke Kenneth Casso... add extra "persistence" bit to svremap instruction
2021-07-15 Luke Kenneth Casso... big intrusive update: merge SVREMAP with SVSTATE, remov...
2021-07-14 Luke Kenneth Casso... update SVSTATE to 64 bit length
2021-07-11 Luke Kenneth Casso... minor reordering of setvl and svshape: svshape is now...
2021-07-11 Luke Kenneth Casso... update svremap instruction to correctly store immediate...
2021-07-11 Luke Kenneth Casso... whoops 0b00002 is not binary
2021-07-11 Luke Kenneth Casso... add SVREMAP new Form / Fields and CSV entry
2021-07-11 Luke Kenneth Casso... add SVREMAP SPR
2021-07-11 Luke Kenneth Casso... rename svremap to svshape
2021-07-11 Luke Kenneth Casso... rename svremap to svshape
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