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[riscv-isa-sim.git] / riscv /
2018-10-09 Luke Kenneth Casso... add explanatory comment tree | commitdiff
2018-10-09 Luke Kenneth Casso... add explanatory comment tree | commitdiff
2018-10-09 Luke Kenneth Casso... start adding explicit twin-predicated branch identifica... tree | commitdiff
2018-10-09 Luke Kenneth Casso... extend sv register file from 64 to 128 after discussion. tree | commitdiff
2018-10-07 Luke Kenneth Casso... override setpc macro so that sv can redirect it in... tree | commitdiff
2018-10-07 Luke Kenneth Casso... swap #ifdef USING_NOREGS so that it is possible to... tree | commitdiff
2018-10-07 Luke Kenneth Casso... add rd bit-setting function tree | commitdiff
2018-10-07 Luke Kenneth Casso... add extra debug printing for c.lwsp tree | commitdiff
2018-10-07 Luke Kenneth Casso... add rvc_swsp_imm sv overload, provides vector unit... tree | commitdiff
2018-10-06 Luke Kenneth Casso... c.swsp and c.fswsp predication and offset enabling tree | commitdiff
2018-10-06 Luke Kenneth Casso... allow x2 (sp) to be redirected in C.LWSP tree | commitdiff
2018-10-06 Luke Kenneth Casso... temporary hack disabling SV in anything other than... tree | commitdiff
2018-10-06 Luke Kenneth Casso... whoops inverted ldsp and lwsp immediates tree | commitdiff
2018-10-06 Luke Kenneth Casso... create ldsp immediate offset overrides tree | commitdiff
2018-10-06 Luke Kenneth Casso... add in predication for immediate, for C.LWSP tree | commitdiff
2018-10-05 Luke Kenneth Casso... reorganise src and dest vector-element offsets tree | commitdiff
2018-10-05 Luke Kenneth Casso... add srcoffs and destoffs sv state, alter CSRs tree | commitdiff
2018-10-04 Luke Kenneth Casso... reorganise twin-predication tree | commitdiff
2018-10-04 Luke Kenneth Casso... big reorganisation to support twin-predication tree | commitdiff
2018-10-03 Luke Kenneth Casso... add in twin-predication identification tree | commitdiff
2018-10-03 Luke Kenneth Casso... decided not to change the behaviour of LOAD/STORE tree | commitdiff
2018-10-02 Luke Kenneth Casso... start work on parallelsing LOAD, pass in parameter... tree | commitdiff
2018-10-02 Luke Kenneth Casso... debug print for floating-point regs tree | commitdiff
2018-10-01 Luke Kenneth Casso... add comment explaining why invert isnt done in zeroing... tree | commitdiff
2018-10-01 Luke Kenneth Casso... add comment explaining use of insn._rd() in zeroing tree | commitdiff
2018-10-01 Luke Kenneth Casso... whoops vloop continuation logic the wrong way round tree | commitdiff
2018-09-30 Luke Kenneth Casso... update template comment tree | commitdiff
2018-09-30 Luke Kenneth Casso... lots of debugging of predication, found other errors tree | commitdiff
2018-09-30 Luke Kenneth Casso... add sv support for zeroing predication in dest register tree | commitdiff
2018-09-30 Luke Kenneth Casso... add in predication to sv instruction execution tree | commitdiff
2018-09-30 Luke Kenneth Casso... start linking in predication into sv tree | commitdiff
2018-09-30 Luke Kenneth Casso... use an alternative logic for detecting scalar / loop-end tree | commitdiff
2018-09-30 Luke Kenneth Casso... fix code template for when SPIKE_SIMPLEV is not defined tree | commitdiff
2018-09-29 Luke Kenneth Casso... fix bug in sv template where FRS2 was checking rs3 tree | commitdiff
2018-09-29 Luke Kenneth Casso... add checks for RVC registers to sv template tree | commitdiff
2018-09-29 Luke Kenneth Casso... add sv_insn_t overloads for rvc registers tree | commitdiff
2018-09-29 Luke Kenneth Casso... also arrange for id_regs.py to identify compressed... tree | commitdiff
2018-09-29 Luke Kenneth Casso... a LOT of debugging and fixing, sv loop actually working tree | commitdiff
2018-09-29 Luke Kenneth Casso... move SV CSRs to user-read-write tree | commitdiff
2018-09-29 Luke Kenneth Casso... add near-duplicate of SV CFG REG CSRs, for predication tree | commitdiff
2018-09-29 Luke Kenneth Casso... add implementation of CSR SV CFG regs 0-7 tree | commitdiff
2018-09-29 Luke Kenneth Casso... assign SV REG CSRs (using new union ability) tree | commitdiff
2018-09-29 Luke Kenneth Casso... make sv csr tables a union so they can be assigned... tree | commitdiff
2018-09-29 Luke Kenneth Casso... add support for CSR_SVVL to CSRRWI as well tree | commitdiff
2018-09-29 Luke Kenneth Casso... fix bug in CSR set SVVL: val has already been looked up tree | commitdiff
2018-09-29 Luke Kenneth Casso... add stub for SV REG configs tree | commitdiff
2018-09-29 Luke Kenneth Casso... stop a compiler warning tree | commitdiff
2018-09-29 Luke Kenneth Casso... reorganise from moving sv_pred_* and sv_reg_* tables... tree | commitdiff
2018-09-29 Luke Kenneth Casso... have to move SV CSRs into processor_t tree | commitdiff
2018-09-29 Luke Kenneth Casso... add 8 CSRs for registers and predication each tree | commitdiff
2018-09-29 Luke Kenneth Casso... whoops dont need separate SVSETVL/SVGETVL CSRs tree | commitdiff
2018-09-29 Luke Kenneth Casso... revert addition of svsetvl as an actual opcode, add... tree | commitdiff
2018-09-29 Luke Kenneth Casso... Revert "sv setvl as a csr not going to work, add getvl... tree | commitdiff
2018-09-29 Luke Kenneth Casso... Revert "manually add svsetvl instruction" tree | commitdiff
2018-09-28 Luke Kenneth Casso... manually add svsetvl instruction tree | commitdiff
2018-09-28 Luke Kenneth Casso... sv setvl as a csr not going to work, add getvl only tree | commitdiff
2018-09-27 Luke Kenneth Casso... adding sv vector length CSR to processor state, and... tree | commitdiff
2018-09-27 Luke Kenneth Casso... add sv predication function tree | commitdiff
2018-09-26 Luke Kenneth Casso... save some cpu cycles by |ing the checks for vectorop... tree | commitdiff
2018-09-26 Luke Kenneth Casso... whoops vectorop has to be |= not &= to accumulate ... tree | commitdiff
2018-09-26 Luke Kenneth Casso... cache the sv redirected register values on each loop tree | commitdiff
2018-09-26 Luke Kenneth Casso... remembered that the use of sv registers have to be... tree | commitdiff
2018-09-26 Luke Kenneth Casso... clarify comments on (key strategic) sv_insn_t::remap... tree | commitdiff
2018-09-26 Luke Kenneth Casso... actually implement sv register re-mapping tree | commitdiff
2018-09-26 Luke Kenneth Casso... ok this is tricky: an extra parameter has to be passed... tree | commitdiff
2018-09-26 Luke Kenneth Casso... move sv remap function to sv.cc (not inline) tree | commitdiff
2018-09-26 Luke Kenneth Casso... check if register redirection is active, and if vectori... tree | commitdiff
2018-09-26 Luke Kenneth Casso... comment why sv_insn_t is set up the way it is; add... tree | commitdiff
2018-09-26 Luke Kenneth Casso... include auto-generated identification of use of registe... tree | commitdiff
2018-09-26 Luke Kenneth Casso... shuffle things around a bit for sv, put rv32/64_name... tree | commitdiff
2018-09-25 Luke Kenneth Casso... add decode.h header to sv.h tree | commitdiff
2018-09-25 Luke Kenneth Casso... rename sv vlen to sv voffs, add csr and reg tables tree | commitdiff
2018-09-25 Luke Kenneth Casso... add reference to vector length in sv tree | commitdiff
2018-09-25 Luke Kenneth Casso... use sv_insn_t class in instruction template tree | commitdiff
2018-09-25 Luke Kenneth Casso... add sv_insn_t class (inherits from insn_t) tree | commitdiff
2018-09-25 Luke Kenneth Casso... argh cant virtualise rd/rs1-3, due to union usage with... tree | commitdiff
2018-09-25 Luke Kenneth Casso... sv: rd, rs1/2/3 become virtual so that sv_insn_t can... tree | commitdiff
2018-09-25 Luke Kenneth Casso... clarify sv cam table tree | commitdiff
2018-09-24 Luke Kenneth Casso... define CSR and register tables for SV tree | commitdiff
2018-09-06 Tim NewsomeMerge pull request #235 from riscv/sba tree | commitdiff
2018-09-05 Tim NewsomeFix cut-and-paste bug in 64-bit SBA loads. tree | commitdiff
2018-08-24 Tim NewsomeAdd dummy custom debug registers, to test OpenOCD.... tree | commitdiff
2018-08-24 Andrew WatermanFix several disassembler bugs tree | commitdiff
2018-08-23 Andrew WatermanAdd --disable-dtb option to suppress writing the DTB... tree | commitdiff
2018-08-22 Andrew WatermanMake IRQ_COP read-only/undelegable unless coprocessor... tree | commitdiff
2018-08-21 Andrew WatermanInstantiate disassembler after max_xlen is known tree | commitdiff
2018-08-18 Andrew WatermanDon't increment instret immediately after it is written... tree | commitdiff
2018-08-10 Tim NewsomeFix 2 trigger corner cases. (#229) tree | commitdiff
2018-07-31 Andrew WatermanMake sstatus.MXR readable tree | commitdiff
2018-07-23 SeungRyeol LeeFix using the uninitialized disassemble object. (#220) tree | commitdiff
2018-07-10 Andrew WatermanRefactor and fix LR/SC implementation (#217) tree | commitdiff
2018-06-12 Tim NewsomeMerge pull request #212 from riscv/hartsel tree | commitdiff
2018-06-11 Tim NewsomeUpdate debug_defines.h tree | commitdiff
2018-05-31 Andy WrightPut simif_t declaration in its own file. (#209) tree | commitdiff
2018-05-18 Prashanth MundkurFix install of missed header. (#207) tree | commitdiff
2018-05-18 Prashanth MundkurExtract out device-tree generation and compilation... tree | commitdiff
2018-05-04 Andrew WatermanRevert "C.LWSP and C.LDSP with rd=0 are legal instructions" tree | commitdiff
2018-05-04 Andrew WatermanC.LWSP and C.LDSP with rd=0 are legal instructions tree | commitdiff
2018-05-01 Andrew WatermanFix commit log for serializing instructions tree | commitdiff
2018-04-30 Andrew WatermanOnly break out of the simulator loop on WFI, not on... tree | commitdiff
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Simple-V augmented version of spike