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set dram_clk_freq = 100.0e6 for orangecrab
[ls2.git]
/
simsoc.ys
2022-04-15
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2022-04-15
Luke Kenneth Casso...
checking simulation of Async DDR3
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2022-04-04
Luke Kenneth Casso...
disable ethmac for now, pass firmware.hex to cypress...
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2022-04-02
Raptor Engineering...
Add 10/100 MAC pins for Versa boards and enable MAC
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2022-03-31
Luke Kenneth Casso...
whitespace cleanup
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2022-03-02
Luke Kenneth Casso...
lots of comments in the yosys script file
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2022-03-01
Luke Kenneth Casso...
add new icarus-versa-ecp5 platform in ls2.py
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2022-02-28
Luke Kenneth Casso...
increase timescale of icarus simulation
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2022-02-28
Luke Kenneth Casso...
use a slightly different yosys initialisation sequence...
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2022-02-28
Luke Kenneth Casso...
fix memory issue in yosys synth for icarus
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2022-02-28
Luke Kenneth Casso...
add icarus simulation of ls2 with DDR3 and ECP5 models
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