misc: Delete the now unnecessary create methods.
[gem5.git] / src / arch / sparc / tlb.cc
2020-10-30 Gabe Blackmisc: Delete the now unnecessary create methods.
2020-10-27 Giacomo Travagliniarch-sparc: Replace any getDTBPtr/getITBPtr usage
2020-10-14 Gabe Blackmisc: Standardize the way create() constructs SimObjects.
2020-07-04 Bobby R. Brucemisc: Merged m5ops_base hotfix into develop
2020-06-09 Gabe Blackarch,cpu,dev,sim,mem: Collect System thread elements...
2020-03-19 Gabe Blacksparc: Make translateFunctional ignore alignment and...
2020-03-09 Gabe Blacksparc: Implement translateFunctional in the TLB class.
2020-03-08 Gabe Blacksparc: Delete some commented out code in the TLB.
2020-03-04 Gabe Blackarch,cpu,mem: Replace the mmmapped IPR mechanism with...
2020-02-26 Bobby R. Brucemisc: merge branch 'release-staging-v19.0.0.0' into...
2020-02-24 Bobby R. Brucemisc: Merged release-staging-v19.0.0.0 into develop
2020-02-18 Gabe Blacksparc: Delete authors lists from sparc files.
2019-09-13 Gabe Blacksparc: Fix a warning/error in tlb.cc.
2019-04-30 Gabe Blacksparc: Move the interrupt types out of isa_traits.hh...
2018-10-12 Gabe Blacksparc: Use big endian packet accessors.
2018-06-11 Giacomo Travaglinimisc: Using smart pointers for memory Requests
2018-03-27 Gabe Blacksparc: Add some missing M5_FALLTHROUGHs and breaks.
2018-02-24 Khaliquesparc: Fix FS Checkpoint loading
2017-12-22 Gabe Blackarch,cpu: "virtualize" the TLB interface.
2016-11-09 Brandon Potterstyle: [patch 1/22] use /r/3648/ to reorganize includes
2015-09-30 Mitch Hayengaisa,cpu: Add support for FS SMT Interrupts
2015-07-07 Andreas Sandbergsim: Refactor the serialization base class
2015-05-05 Andreas Sandbergmem, cpu: Add a separate flag for strictly ordered...
2014-10-16 Andreas Hanssonarch: Use shared_ptr for all Faults
2014-06-01 Steve Reinhardtstyle: eliminate equality tests with true and false stable_2014_08_26
2013-10-15 Andreas Sandbergmem: Rename the ASI_BITS flag field in Request
2013-06-03 Andreas Sandbergarch: Create a method to finalize physical addresses
2013-01-07 Andreas Sandbergarch: Add support for invalidating TLBs when draining
2012-08-28 Andreas HanssonClock: Add a Cycles wrapper class and use where applicable
2012-03-09 Geoffrey BlakeCheckerCPU: Add function stubs to non-ARM ISA source...
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Gabe BlackMerge with main repository.
2012-01-29 Gabe BlackYet another merge with the main repository.
2012-01-28 Gabe BlackMerge with the main repo.
2012-01-16 Gabe BlackMerge yet again with the main repository.
2012-01-07 Gabe BlackAnother merge with the main repository.
2012-01-07 Gabe BlackMerge with the main repository again.
2012-01-07 Gabe BlackMerge with main repository.
2011-10-13 Gabe BlackSPARC: Remove the last checks of FULL_SYSTEM.
2011-10-10 Gabe BlackSPARC: Turn on handleIprRead and handleIprWrite in...
2011-06-20 Korey Sewellsparc: init. cache state in TLB
2011-04-15 Nathan Binkerttrace: reimplement the DTRACE function so it doesn...
2011-04-15 Nathan Binkertincludes: sort all includes
2011-03-02 Gabe BlackSpelling: Fix the a spelling error by changing mmaped...
2011-01-03 Steve ReinhardtMake commenting on close namespace brackets consistent.
2010-11-11 Gabe BlackSPARC: Clean up some historical style issues.
2010-09-14 Gabe BlackFaults: Pass the StaticInst involved, if any, to a...
2010-08-13 Gabe BlackMerge with head.
2010-08-13 Gabe BlackCPU: Tidy up endianness handling for mmapped "IPR"s.
2009-08-03 Derek HowerAutomated merge with ssh://hg@m5sim.org/m5
2009-08-02 Steve ReinhardtClean up some inconsistencies with Request flags.
2009-07-13 Derek Howermerge
2009-07-10 Gabe BlackSPARC: Fold the MiscRegFile all the way into the ISA...
2009-04-09 Nathan Binkerttlb: More fixing of unified TLB
2009-04-09 Gabe Blacktlb: Don't separate the TLB classes into an instruction...
2009-04-06 Gabe BlackMerge ARM into the head. ARM will compile but may not...
2009-02-25 Gabe BlackCPU: Implement translateTiming which defers to translat...
2009-02-25 Gabe BlackISA: Replace the translate functions in the TLBs with...
2009-01-31 Ali SaidiErrors: Use the correct panic/warn/fatal/info message...
2008-11-10 Nathan Binkertmem: update stuff for changes to Packet and Request
2008-10-21 Nathan Binkertstyle: Use the correct m5 style for things relating...
2008-10-12 Gabe BlackCPU: Eliminate the get_vec function.
2008-09-28 Nathan Binkertgcc: Add extra parens to quell warnings.
2008-09-24 Nathan Binkertsparc: Fix style, create a helper function for translation.
2008-02-27 Steve ReinhardtAutomated merge with ssh://daystrom.m5sim.org//repo/m5
2008-02-27 Gabe BlackTLB: Make a TLB base class and put a virtual demapPage...
2008-01-01 Gabe BlackSPARC: Fix a bug where the TLB would match against...
2007-12-01 Gabe BlackSPARC: Fixes for invalidateAll and demapAll in the...
2007-11-20 Gabe BlackMerge with head.
2007-11-20 Ali SaidiSerialization: Serialize SPARC PTEs last so their nameO...
2007-10-31 Steve ReinhardtMerge in bus DPRINTF changes.
2007-10-03 Gabe BlackMerge with head.
2007-09-28 Ali SaidiRename cycles() function to ticks()
2007-08-30 Miles Kaufmannparams: Deprecate old-style constructors; update most...
2007-08-28 Gabe BlackMerge with head.
2007-08-27 Gabe BlackAddress Translation: Make SE mode use an actual TLB...
2007-08-27 Gabe BlackSPARC: Make sure unaligned access are caught on cached...
2007-08-21 Gabe BlackMerge with head.
2007-08-19 Gabe BlackMerge with head.
2007-08-14 Gabe BlackMerge with head.
2007-08-13 Gabe BlackSPARC: Move tlb state into the tlb.
2007-08-13 Gabe BlackSPARC: Make the spill and fill handlers use the correct...
2007-08-05 Gabe BlackMerge with head.
2007-08-03 Steve Reinhardtmerge from head
2007-08-01 Nathan Binkertmerge: mips fix to getArgument
2007-08-01 Gabe BlackMerge with head.
2007-08-01 Gabe BlackMerge with head.
2007-07-31 Steve ReinhardtMerge from head.
2007-07-29 Steve ReinhardtMerge Gabe's changes from head.
2007-07-29 Nathan Binkertmerge: style.py fix
2007-07-29 Nathan Binkertmerge whitespace fixes
2007-07-29 Nathan Binkertmerge whitespace changes
2007-07-27 Nathan BinkertMerge python and x86 changes with cache branch
2007-07-24 Gabe BlackMerge with head.
2007-07-24 Nathan BinkertMajor changes to how SimObjects are created and initial...
2007-07-22 Steve ReinhardtMerge from head.
2007-07-22 Steve ReinhardtMerge more changes in from head.
2007-07-16 Steve ReinhardtMerge from head.
2007-07-14 Steve ReinhardtMerge from head.
2007-07-14 Steve ReinhardtMerge of DPRINTF fixes from head.
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