git.libre-soc.org Git - ls2.git/history

2022-02-22	Luke Kenneth Casso...	xdr=4 missing on ddr3 platform request for VERSA_ECP5	blob \| commitdiff \| raw
2022-02-21	Luke Kenneth Casso...	* use readl and writel for accessing memory	blob \| commitdiff \| raw \| diff to current
2022-02-20	Luke Kenneth Casso...	for simulatio keep the simulated dram in the	blob \| commitdiff \| raw \| diff to current
2022-02-20	Luke Kenneth Casso...	add fake (sim) DRAM from gram library	blob \| commitdiff \| raw \| diff to current
2022-02-19	Luke Kenneth Casso...	match up dram initialisation parameters	blob \| commitdiff \| raw \| diff to current
2022-02-19	Luke Kenneth Casso...	hm -abc9 seems to be working, and without -nowidelut	blob \| commitdiff \| raw \| diff to current
2022-02-18	Luke Kenneth Casso...	add DRAM class to DDR3Soc	blob \| commitdiff \| raw \| diff to current
2022-02-18	Luke Kenneth Casso...	add FPGA argument to DDR3SoC	blob \| commitdiff \| raw \| diff to current
2022-02-18	Luke Kenneth Casso...	add microwatt console lib and #includes	blob \| commitdiff \| raw \| diff to current
2022-02-18	Luke Kenneth Casso...	make cpu optional (test purposes), make bios optional,	blob \| commitdiff \| raw \| diff to current
2022-02-16	Luke Kenneth Casso...	remove minerva cpu	blob \| commitdiff \| raw \| diff to current
2022-02-16	Luke Kenneth Casso...	drop clock frequency to 25 mhz and disable abc9 (it...	blob \| commitdiff \| raw \| diff to current
2022-02-16	Luke Kenneth Casso...	update ECP5 PLL to accept parameters for setting arbitr...	blob \| commitdiff \| raw \| diff to current
2022-02-16	Luke Kenneth Casso...	* add uart_pins to UART16550 peripheral so they get...	blob \| commitdiff \| raw \| diff to current
2022-02-16	Luke Kenneth Casso...	* disable DDR3 for now	blob \| commitdiff \| raw \| diff to current
2022-02-15	Luke Kenneth Casso...	connect up stall signals (fake) for WB Classic compliance	blob \| commitdiff \| raw \| diff to current
2022-02-15	Luke Kenneth Casso...	alternative uart wishbone mapping which just takes...	blob \| commitdiff \| raw \| diff to current
2022-02-15	Luke Kenneth Casso...	attempt to do 8-bit downconvert on wishbone bus for...	blob \| commitdiff \| raw \| diff to current
2022-02-15	Luke Kenneth Casso...	correct syscon bus address to 0xC000_0000	blob \| commitdiff \| raw \| diff to current
2022-02-15	Luke Kenneth Casso...	add microwatt SYSCON peripheral at 0xc000_0000	blob \| commitdiff \| raw \| diff to current
2022-02-15	Luke Kenneth Casso...	increase size of bootmem	blob \| commitdiff \| raw \| diff to current
2022-02-15	Luke Kenneth Casso...	add interrupt controller module, remove stall feature...	blob \| commitdiff \| raw \| diff to current
2022-02-14	Luke Kenneth Casso...	add external cpu	blob \| commitdiff \| raw \| diff to current
2022-02-14	Luke Kenneth Casso...	convert boot rom to bootmem and get first hello_world...	blob \| commitdiff \| raw \| diff to current
2022-02-14	Luke Kenneth Casso...	add first cut of verilator simulation, over from microwatt	blob \| commitdiff \| raw \| diff to current
2022-02-14	Luke Kenneth Casso...	add verilog build option, make DDR3 PHY optional, add...	blob \| commitdiff \| raw \| diff to current
2022-02-13	Luke Kenneth Casso...	add future sim option (needs Simulated DDR PHY)	blob \| commitdiff \| raw \| diff to current
2022-02-13	Luke Kenneth Casso...	rename examples to src	blob \| commitdiff \| raw \| diff to current

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