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correct pin names for HyperRAMResource, indent spi0 core
[ls2.git]
/
src
/
ls2.py
2022-03-19
Luke Kenneth Casso...
correct pin names for HyperRAMResource, indent spi0...
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2022-03-19
Luke Kenneth Casso...
fixed hyperram pin names which was stopping verilator...
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2022-03-19
Luke Kenneth Casso...
disable hyperram for now (under investigation)
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2022-03-19
Luke Kenneth Casso...
adding in hyperram peripheral
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2022-03-18
Luke Kenneth Casso...
whitespace / module-import / comments / tidyup
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2022-03-18
Luke Kenneth Casso...
beginning to add hyperram module
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2022-03-18
Luke Kenneth Casso...
whitespace cleanup and make SPI core (temporarily)...
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2022-03-17
Luke Kenneth Casso...
work-in-progress on DDR3 firmware. sigh
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2022-03-16
Raptor Engineering...
Add initial Tercel SPI controller
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2022-03-10
Luke Kenneth Casso...
sigh gramWishbone is not WB4-pipeline-burst-compliant
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2022-03-09
Luke Kenneth Casso...
fix WB6to32 downconverter with stall signalling
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2022-03-09
Luke Kenneth Casso...
add stall signal to arbiter, assume nmigen-soc takes
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2022-03-04
Luke Kenneth Casso...
add experimental stall-capable 64-to-32 wishbone converter
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2022-03-01
Luke Kenneth Casso...
add new icarus-versa-ecp5 platform in ls2.py
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2022-02-22
Luke Kenneth Casso...
xdr=4 missing on ddr3 platform request for VERSA_ECP5
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2022-02-21
Luke Kenneth Casso...
* use readl and writel for accessing memory
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2022-02-20
Luke Kenneth Casso...
for simulatio keep the simulated dram in the
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2022-02-20
Luke Kenneth Casso...
add fake (sim) DRAM from gram library
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2022-02-19
Luke Kenneth Casso...
match up dram initialisation parameters
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2022-02-19
Luke Kenneth Casso...
hm -abc9 seems to be working, and without -nowidelut
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2022-02-18
Luke Kenneth Casso...
add DRAM class to DDR3Soc
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2022-02-18
Luke Kenneth Casso...
add FPGA argument to DDR3SoC
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2022-02-18
Luke Kenneth Casso...
add microwatt console lib and #includes
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2022-02-18
Luke Kenneth Casso...
make cpu optional (test purposes), make bios optional,
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2022-02-16
Luke Kenneth Casso...
remove minerva cpu
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2022-02-16
Luke Kenneth Casso...
drop clock frequency to 25 mhz and disable abc9 (it...
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2022-02-16
Luke Kenneth Casso...
update ECP5 PLL to accept parameters for setting arbitr...
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2022-02-16
Luke Kenneth Casso...
* add uart_pins to UART16550 peripheral so they get...
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2022-02-16
Luke Kenneth Casso...
* disable DDR3 for now
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2022-02-15
Luke Kenneth Casso...
connect up stall signals (fake) for WB Classic compliance
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2022-02-15
Luke Kenneth Casso...
alternative uart wishbone mapping which just takes...
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2022-02-15
Luke Kenneth Casso...
attempt to do 8-bit downconvert on wishbone bus for...
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2022-02-15
Luke Kenneth Casso...
correct syscon bus address to 0xC000_0000
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2022-02-15
Luke Kenneth Casso...
add microwatt SYSCON peripheral at 0xc000_0000
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2022-02-15
Luke Kenneth Casso...
increase size of bootmem
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2022-02-15
Luke Kenneth Casso...
add interrupt controller module, remove stall feature...
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2022-02-14
Luke Kenneth Casso...
add external cpu
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2022-02-14
Luke Kenneth Casso...
convert boot rom to bootmem and get first hello_world...
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2022-02-14
Luke Kenneth Casso...
add first cut of verilator simulation, over from microwatt
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2022-02-14
Luke Kenneth Casso...
add verilog build option, make DDR3 PHY optional, add...
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2022-02-13
Luke Kenneth Casso...
add future sim option (needs Simulated DDR PHY)
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2022-02-13
Luke Kenneth Casso...
rename examples to src
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