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sort out subvl unit test with expected results
[openpower-isa.git]
/
src
/
openpower
/
consts.py
2022-02-28
Dmitry Selyutin
openpower.consts: replace botchify with metaclass
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2022-02-28
Dmitry Selyutin
openpower.const: switch to enum class
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2022-01-19
Luke Kenneth Casso...
add spr-to-state conversion, and support for state1...
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2021-09-04
Luke Kenneth Casso...
redo SVP64 RM Decode to new CTR-Test Mode (svstep not...
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2021-08-11
Luke Kenneth Casso...
corrections to SVP64 Branch Conditional
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2021-08-10
Luke Kenneth Casso...
corrections to SVP64 Branch RM Mode decoding
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2021-08-08
Luke Kenneth Casso...
add start of SVP64ASM encoder for sv.bc and sv.bclr
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2021-08-01
Luke Kenneth Casso...
bit of a big update, remove all bit-reversed LD operati...
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2021-07-15
Luke Kenneth Casso...
stop using MSR vfirst bit, move to SVSTATE bit 63 instead
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2021-07-08
Luke Kenneth Casso...
add in extra "vertical" mode into SVP64 setvl
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2021-06-23
Luke Kenneth Casso...
add start of bit-reverse mode for LD/ST to SVP64 encode...
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2021-06-19
Luke Kenneth Casso...
add "reverse-gear" mode to mapreduce in SVP64
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2021-05-04
Luke Kenneth Casso...
copy over svstate from core state in PowerDecoder2
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2021-04-23
Luke Kenneth Casso...
move Regfile enums here
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2021-04-23
Luke Kenneth Casso...
move Regfile enums here
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2021-04-23
Luke Kenneth Casso...
move consts from soc
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