corrections to SVP64 Branch RM Mode decoding
[openpower-isa.git] / src / openpower / consts.py
2021-08-10 Luke Kenneth Casso... corrections to SVP64 Branch RM Mode decoding
2021-08-08 Luke Kenneth Casso... add start of SVP64ASM encoder for sv.bc and sv.bclr
2021-08-01 Luke Kenneth Casso... bit of a big update, remove all bit-reversed LD operati...
2021-07-15 Luke Kenneth Casso... stop using MSR vfirst bit, move to SVSTATE bit 63 instead
2021-07-08 Luke Kenneth Casso... add in extra "vertical" mode into SVP64 setvl
2021-06-23 Luke Kenneth Casso... add start of bit-reverse mode for LD/ST to SVP64 encode...
2021-06-19 Luke Kenneth Casso... add "reverse-gear" mode to mapreduce in SVP64
2021-05-04 Luke Kenneth Casso... copy over svstate from core state in PowerDecoder2
2021-04-23 Luke Kenneth Casso... move Regfile enums here
2021-04-23 Luke Kenneth Casso... move Regfile enums here
2021-04-23 Luke Kenneth Casso... move consts from soc