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swap complicated bits, simplify ISACaller, reduce indent level
[openpower-isa.git]
/
src
/
openpower
/
decoder
/
isa
/
caller.py
2021-07-05
Luke Kenneth Casso...
debugging SVSHAPE for REMAP
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2021-07-05
Luke Kenneth Casso...
add in use of SVSHAPE in ISACaller. untested (no damage...
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2021-07-05
Luke Kenneth Casso...
add last_op_svshape flag to ISACaller
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2021-07-05
Luke Kenneth Casso...
add svremap manual instruction (Primary Opcode 22,...
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2021-07-05
Luke Kenneth Casso...
add SVSHAPE class, starting to add to ISACaller
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2021-06-27
Luke Kenneth Casso...
add new (experimental) ffmadds and ffmsubs, for FFT...
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2021-06-27
Luke Kenneth Casso...
override logic for getting FRS in SVP64 FFT mode
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2021-06-26
Luke Kenneth Casso...
add LD bit-reversed unit test
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2021-06-26
Luke Kenneth Casso...
move D const update to after picking up main input...
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2021-06-23
Luke Kenneth Casso...
add VL and srcstep to ISACaller namespace
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2021-06-19
Luke Kenneth Casso...
set regfile in ISACaller equal to length of initial...
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2021-06-19
Luke Kenneth Casso...
add mapreduce "reverse gear" unit tests
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2021-06-19
Luke Kenneth Casso...
add mapreduce "reverse gear" to PowerDecoder2. gets...
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2021-06-09
Luke Kenneth Casso...
add first scalar mapreduce SVP64 example
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2021-06-02
Luke Kenneth Casso...
whoops sorting SPRs, stop that for now
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2021-06-01
Luke Kenneth Casso...
bit more memdump debugging on qemu sim
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2021-06-01
Luke Kenneth Casso...
comment cleanup, record last LD/ST address in simulator
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2021-05-30
Luke Kenneth Casso...
add "normal" element-strided LD/ST decode/support to...
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2021-05-29
Luke Kenneth Casso...
add unit-strided LD/ST ISACaller SVP64 unit test
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2021-05-27
Luke Kenneth Casso...
whoops yield in setup_one ISACaller
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2021-05-27
Luke Kenneth Casso...
slightly messy: qemu goes haywire at the last instruction.
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2021-05-26
Lauri Kasanen
Undo log in isa/caller reg dump
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2021-05-25
Lauri Kasanen
Switch to log in isa/caller
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2021-05-24
Luke Kenneth Casso...
add nop support to ISACaller
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2021-05-21
Luke Kenneth Casso...
return register values from GPR.dump in ISACaller
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2021-05-21
Luke Kenneth Casso...
return dump of SPRs (to be used for saving, later)
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2021-05-21
Luke Kenneth Casso...
add dump of SPRs to pypowersim
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2021-05-21
Luke Kenneth Casso...
add option to run without a disassembly listing to...
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2021-05-19
Luke Kenneth Casso...
resolve merge conflicts, effectively reverting "verbose...
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2021-05-18
Luke Kenneth Casso...
revert register reordering in ISACaller
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2021-05-17
Luke Kenneth Casso...
update reg sort order in ISACaller
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2021-05-17
Luke Kenneth Casso...
must not add to read regs unless in the authorised...
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2021-05-17
Luke Kenneth Casso...
add new RC reg to get pywriter to build
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2021-05-15
Luke Kenneth Casso...
extra debug print
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2021-05-15
Luke Kenneth Casso...
whoops initialise FPRs from GPRs in ISACaller
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2021-05-15
Luke Kenneth Casso...
add fmr test and associated decoder (optional with...
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2021-05-15
Luke Kenneth Casso...
add new fp load / store with update unit test
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2021-05-14
Luke Kenneth Casso...
add FP load test lfsx
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2021-05-14
Luke Kenneth Casso...
add FRA ISACaller name decoding
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2021-05-14
Luke Kenneth Casso...
add FPR (FP Regfile) to ISACaller
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2021-05-14
Luke Kenneth Casso...
add FRA-FRT fp reg names to ISACaller parser
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2021-05-10
Luke Kenneth Casso...
testing load misaligned
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2021-05-10
Luke Kenneth Casso...
save SVSRR0 in trap, if SVP64 mode enabled
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2021-05-10
Luke Kenneth Casso...
create new call_trap function in ISACaller
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2021-05-10
Luke Kenneth Casso...
add catch of MemException in ISACaller to raise unalign...
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2021-04-25
Cesar Strauss
Move creation of CR fields to its own class
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2021-04-23
Luke Kenneth Casso...
resolving imports changing over
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2021-04-23
Luke Kenneth Casso...
add pseudo and isa
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