| 2021-09-28 |
Luke Kenneth Casso... | move FPDIV, FPMUL (etc) to ISAFPHelpers class |
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| 2021-09-25 |
Luke Kenneth Casso... | inherit ISACallerHelper in ISACaller |
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| 2021-09-22 |
Luke Kenneth Casso... | take a copy of SPRs so they are not modified by ISACaller |
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| 2021-08-21 |
Luke Kenneth Casso... | set XLEN=64 in ISACaller |
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| 2021-08-15 |
Luke Kenneth Casso... | take copy of GPR/FPR inputs into ISACaller |
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| 2021-08-15 |
Luke Kenneth Casso... | sv.bc test jumping to wrong location (offset 0xc not... |
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| 2021-08-14 |
Luke Kenneth Casso... | create an end loop condition which tells the sv.bc... |
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| 2021-08-14 |
Luke Kenneth Casso... | end loop condition in svp64 bc pseudo-code |
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| 2021-08-14 |
Luke Kenneth Casso... | messy resolution of sv.bc testing, early-out detection. |
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| 2021-08-12 |
Luke Kenneth Casso... | add ctr_ok and cond_ok to namespace to be able |
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| 2021-08-11 |
Luke Kenneth Casso... | whoops test for sv.bc* matched accidentally, use explic... |
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| 2021-08-11 |
Luke Kenneth Casso... | redirect sv.bc to new svbranch in ISACaller |
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| 2021-08-11 |
Luke Kenneth Casso... | corrections to SVP64 Branch Conditional |
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| 2021-08-01 |
Luke Kenneth Casso... | bit of a big update, remove all bit-reversed LD operati... |
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| 2021-07-28 |
Luke Kenneth Casso... | argh, have LD-bitreverse select the offset from RA... |
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| 2021-07-28 |
Luke Kenneth Casso... | code comments |
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| 2021-07-27 |
Luke Kenneth Casso... | argh, LD/ST using DS has to be computed differently. |
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| 2021-07-24 |
Luke Kenneth Casso... | add DS-Form support for sv.std |
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| 2021-07-24 |
Luke Kenneth Casso... | added an extra SVP64 instruction, svstep, to replace... |
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| 2021-07-24 |
Luke Kenneth Casso... | add ability to get current SVSHAPE indices into a register, |
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| 2021-07-23 |
Luke Kenneth Casso... | "fix" fdmadd DCT mul-add-sub unit test with values... |
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| 2021-07-20 |
Luke Kenneth Casso... | add inner sub-loop testing from svstep Rc=1 |
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| 2021-07-19 |
Luke Kenneth Casso... | bit of a reorg, adding option to test end of inner... |
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| 2021-07-16 |
Luke Kenneth Casso... | add fsins and fcoss to simulator |
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| 2021-07-15 |
Luke Kenneth Casso... | enable use of svremap "persist" mode, remove 4 instruct... |
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| 2021-07-15 |
Luke Kenneth Casso... | stop using MSR vfirst bit, move to SVSTATE bit 63 instead |
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| 2021-07-15 |
Luke Kenneth Casso... | big intrusive update: merge SVREMAP with SVSTATE, remov... |
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| 2021-07-14 |
Luke Kenneth Casso... | update SVSTATE to 64 bit length |
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| 2021-07-13 |
Luke Kenneth Casso... | change order of log printout for "writing gpr NN" |
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| 2021-07-11 |
Luke Kenneth Casso... | add svremap instruction into ISACaller |
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| 2021-07-11 |
Luke Kenneth Casso... | add SVREMAP SPR to ISACaller and parser |
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| 2021-07-11 |
Luke Kenneth Casso... | add SVREMAP SPR |
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| 2021-07-11 |
Luke Kenneth Casso... | rename svremap to svshape |
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| 2021-07-10 |
Luke Kenneth Casso... | more generic allow fft mode 2nd output detection. ... |
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| 2021-07-08 |
Luke Kenneth Casso... | end SVP64 "Vertical First" mode on rollover when end... |
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| 2021-07-08 |
Luke Kenneth Casso... | add CR0 setting and unit test on svstep |
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| 2021-07-08 |
Luke Kenneth Casso... | whoops must not reset last_op_svstate except when out... |
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| 2021-07-08 |
Luke Kenneth Casso... | testing new setvl "svstep" mode |
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| 2021-07-08 |
Luke Kenneth Casso... | add ability to explicitly increment SVSTATE srcstep... |
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| 2021-07-07 |
Luke Kenneth Casso... | get butterfly RADIX2 SVP64 example working, breaks... |
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| 2021-07-06 |
Luke Kenneth Casso... | when REMAP shape is zero, skip it in ISACaller. |
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| 2021-07-06 |
Luke Kenneth Casso... | add FFT SHAPE pseudocode in svremap, and a schedule... |
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| 2021-07-05 |
Luke Kenneth Casso... | fix svremap field offsets |
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| 2021-07-05 |
Luke Kenneth Casso... | whoops, REMAP inverted |
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| 2021-07-05 |
Luke Kenneth Casso... | debug of SVP64 REMAP |
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| 2021-07-05 |
Luke Kenneth Casso... | debugging SVSHAPE for REMAP |
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| 2021-07-05 |
Luke Kenneth Casso... | add in use of SVSHAPE in ISACaller. untested (no damage... |
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| 2021-07-05 |
Luke Kenneth Casso... | add last_op_svshape flag to ISACaller |
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| 2021-07-05 |
Luke Kenneth Casso... | add svremap manual instruction (Primary Opcode 22,... |
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| 2021-07-05 |
Luke Kenneth Casso... | add SVSHAPE class, starting to add to ISACaller |
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| 2021-06-27 |
Luke Kenneth Casso... | add new (experimental) ffmadds and ffmsubs, for FFT... |
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| 2021-06-27 |
Luke Kenneth Casso... | override logic for getting FRS in SVP64 FFT mode |
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| 2021-06-26 |
Luke Kenneth Casso... | add LD bit-reversed unit test |
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| 2021-06-26 |
Luke Kenneth Casso... | move D const update to after picking up main input... |
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| 2021-06-23 |
Luke Kenneth Casso... | add VL and srcstep to ISACaller namespace |
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| 2021-06-19 |
Luke Kenneth Casso... | set regfile in ISACaller equal to length of initial... |
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| 2021-06-19 |
Luke Kenneth Casso... | add mapreduce "reverse gear" unit tests |
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| 2021-06-19 |
Luke Kenneth Casso... | add mapreduce "reverse gear" to PowerDecoder2. gets... |
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| 2021-06-09 |
Luke Kenneth Casso... | add first scalar mapreduce SVP64 example |
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| 2021-06-02 |
Luke Kenneth Casso... | whoops sorting SPRs, stop that for now |
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| 2021-06-01 |
Luke Kenneth Casso... | bit more memdump debugging on qemu sim |
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| 2021-06-01 |
Luke Kenneth Casso... | comment cleanup, record last LD/ST address in simulator |
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| 2021-05-30 |
Luke Kenneth Casso... | add "normal" element-strided LD/ST decode/support to... |
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| 2021-05-29 |
Luke Kenneth Casso... | add unit-strided LD/ST ISACaller SVP64 unit test |
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| 2021-05-27 |
Luke Kenneth Casso... | whoops yield in setup_one ISACaller |
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| 2021-05-27 |
Luke Kenneth Casso... | slightly messy: qemu goes haywire at the last instruction. |
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| 2021-05-26 |
Lauri Kasanen | Undo log in isa/caller reg dump |
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| 2021-05-25 |
Lauri Kasanen | Switch to log in isa/caller |
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| 2021-05-24 |
Luke Kenneth Casso... | add nop support to ISACaller |
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| 2021-05-21 |
Luke Kenneth Casso... | return register values from GPR.dump in ISACaller |
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| 2021-05-21 |
Luke Kenneth Casso... | return dump of SPRs (to be used for saving, later) |
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| 2021-05-21 |
Luke Kenneth Casso... | add dump of SPRs to pypowersim |
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| 2021-05-21 |
Luke Kenneth Casso... | add option to run without a disassembly listing to... |
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| 2021-05-19 |
Luke Kenneth Casso... | resolve merge conflicts, effectively reverting "verbose... |
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| 2021-05-18 |
Luke Kenneth Casso... | revert register reordering in ISACaller |
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| 2021-05-17 |
Luke Kenneth Casso... | update reg sort order in ISACaller |
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| 2021-05-17 |
Luke Kenneth Casso... | must not add to read regs unless in the authorised... |
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| 2021-05-17 |
Luke Kenneth Casso... | add new RC reg to get pywriter to build |
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| 2021-05-15 |
Luke Kenneth Casso... | extra debug print |
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| 2021-05-15 |
Luke Kenneth Casso... | whoops initialise FPRs from GPRs in ISACaller |
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| 2021-05-15 |
Luke Kenneth Casso... | add fmr test and associated decoder (optional with... |
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| 2021-05-15 |
Luke Kenneth Casso... | add new fp load / store with update unit test |
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| 2021-05-14 |
Luke Kenneth Casso... | add FP load test lfsx |
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| 2021-05-14 |
Luke Kenneth Casso... | add FRA ISACaller name decoding |
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| 2021-05-14 |
Luke Kenneth Casso... | add FPR (FP Regfile) to ISACaller |
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| 2021-05-14 |
Luke Kenneth Casso... | add FRA-FRT fp reg names to ISACaller parser |
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| 2021-05-10 |
Luke Kenneth Casso... | testing load misaligned |
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| 2021-05-10 |
Luke Kenneth Casso... | save SVSRR0 in trap, if SVP64 mode enabled |
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| 2021-05-10 |
Luke Kenneth Casso... | create new call_trap function in ISACaller |
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| 2021-05-10 |
Luke Kenneth Casso... | add catch of MemException in ISACaller to raise unalign... |
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| 2021-04-25 |
Cesar Strauss | Move creation of CR fields to its own class |
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| 2021-04-23 |
Luke Kenneth Casso... | resolving imports changing over |
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| 2021-04-23 |
Luke Kenneth Casso... | add pseudo and isa |
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projects / openpower-isa.git / history