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power_insn: refactor opcode matching
[openpower-isa.git]
/
src
/
openpower
/
decoder
/
isa
/
svshape.py
2022-09-06
Luke Kenneth Casso...
add first functional confirmed unit test for parallel...
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2022-07-10
Luke Kenneth Casso...
Indexed SVSHAPE add bypass mode when dim sizes are 1
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2022-07-10
Luke Kenneth Casso...
fix svindex unit test, experiment setting dimensions
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2022-07-10
Luke Kenneth Casso...
fix SVSHAPE iterator for index case, stop deepcopy
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2022-07-09
Luke Kenneth Casso...
add gpr lookup in Indexed SVSHAPE iterator (no elwidths...
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2022-07-09
Luke Kenneth Casso...
rough unit test ahowing Index REMAP basically functiona...
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2022-07-09
Luke Kenneth Casso...
add support for Indexed mode in SVSHAPE
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2021-08-01
Luke Kenneth Casso...
bit of a big update, remove all bit-reversed LD operati...
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2021-07-31
Luke Kenneth Casso...
add outer-inner RADIX2 iDCT unit test.
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2021-07-31
Luke Kenneth Casso...
add i-DCT SVP64 unit test for outer butterfly
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2021-07-28
Luke Kenneth Casso...
add mode for half-swap, to be combined with LD-bit...
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2021-07-27
Luke Kenneth Casso...
add new DCT inner butterfly shorter COS-gen mode unit...
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2021-07-27
Luke Kenneth Casso...
fix up DCT modes for inner/outer butterfly,
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2021-07-26
Luke Kenneth Casso...
use ydimsz as sub-mode in DCT/FFT butterfly
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2021-07-23
Luke Kenneth Casso...
set up submodes for SVSHAPE, to include DCT butterfly...
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2021-07-11
Luke Kenneth Casso...
rename SVP64REMAP to SVP64SHAPE
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2021-07-06
Luke Kenneth Casso...
add FFT REMAP butterfly unit test
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2021-07-06
Luke Kenneth Casso...
add FFT butterfly iteration to SVSHAPE REMAP class...
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2021-07-05
Luke Kenneth Casso...
debug of SVP64 REMAP
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2021-07-05
Luke Kenneth Casso...
debugging SVSHAPE for REMAP
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2021-07-05
Luke Kenneth Casso...
add in use of SVSHAPE in ISACaller. untested (no damage...
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2021-07-05
Luke Kenneth Casso...
add SVSHAPE class, starting to add to ISACaller
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