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make svstep output srcstep/dststep, basically viota
[openpower-isa.git]
/
src
/
openpower
/
decoder
/
isa
/
test_caller_setvl.py
2022-06-26
Luke Kenneth Casso...
make svstep output srcstep/dststep, basically viota
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2021-07-24
Luke Kenneth Casso...
added an extra SVP64 instruction, svstep, to replace...
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2021-07-24
Luke Kenneth Casso...
add ability to get current SVSHAPE indices into a register,
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2021-07-20
Luke Kenneth Casso...
add inner sub-loop testing from svstep Rc=1
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2021-07-19
Luke Kenneth Casso...
bit of a reorg, adding option to test end of inner...
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2021-07-15
Luke Kenneth Casso...
stop using MSR vfirst bit, move to SVSTATE bit 63 instead
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2021-07-15
Luke Kenneth Casso...
add extra "persistence" bit to svremap instruction
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2021-07-15
Luke Kenneth Casso...
big intrusive update: merge SVREMAP with SVSTATE, remov...
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2021-07-14
Luke Kenneth Casso...
subtract one from SVi field for setvl assembler
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2021-07-11
Luke Kenneth Casso...
add svremap instruction into ISACaller
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2021-07-09
Luke Kenneth Casso...
comments in unit test
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2021-07-09
Luke Kenneth Casso...
add Vertical-First explicit branch-loop using svstep...
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2021-07-08
Luke Kenneth Casso...
end SVP64 "Vertical First" mode on rollover when end...
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2021-07-08
Luke Kenneth Casso...
add CR0 setting and unit test on svstep
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2021-07-08
Luke Kenneth Casso...
test MSR.SVF bit set after setvl Vertical-First mode set
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2021-07-08
Luke Kenneth Casso...
testing new setvl "svstep" mode
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2021-07-08
Luke Kenneth Casso...
add ability to explicitly increment SVSTATE srcstep...
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2021-07-08
Luke Kenneth Casso...
add in extra "vertical" mode into SVP64 setvl
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2021-04-23
Luke Kenneth Casso...
resolving imports changing over
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2021-04-23
Luke Kenneth Casso...
add pseudo and isa
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