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power_insn: refactor opcode matching
[openpower-isa.git]
/
src
/
openpower
/
decoder
/
isa
/
test_caller_svp64_ldst.py
2022-08-12
Luke Kenneth Casso...
remove use of sv ld shifted, replace with els, deprecat...
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2022-08-12
Luke Kenneth Casso...
remove use of sv.lfssh, deprecate the unit test
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2022-07-30
Luke Kenneth Casso...
fix LDST immed using EXTRA2 not EXTRA3 in tests to...
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2022-07-05
Andrey Miroshnikov
convert test_caller_svp64_ldst.py to new vector numberi...
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2022-06-26
Luke Kenneth Casso...
again fix number of arguments to svremap,
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2021-08-01
Luke Kenneth Casso...
bit of a big update, remove all bit-reversed LD operati...
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2021-08-01
Luke Kenneth Casso...
add LD-half-swap for i-DCT which does not work. redesig...
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2021-07-28
Luke Kenneth Casso...
got DCT LD-bit-rev demo operational in unit test
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2021-07-28
Luke Kenneth Casso...
fix LD/ST bitreverse with Matrix REMAP to instead be...
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2021-07-28
Luke Kenneth Casso...
argh, have LD-bitreverse select the offset from RA...
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2021-07-22
Luke Kenneth Casso...
add hybrid LD-ST-bitreverse with REMAP as an experiment
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2021-07-22
Luke Kenneth Casso...
corrections to SVP64 LD/ST unit tests
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2021-07-17
Luke Kenneth Casso...
add FP LOAD bit-reversed operations to ISACaller simulator
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2021-06-29
Luke Kenneth Casso...
re-enable accidentally-disabled sv ld/st tests
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2021-06-26
Luke Kenneth Casso...
add LD bit-reversed unit test
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2021-05-30
Luke Kenneth Casso...
add "normal" element-strided LD/ST decode/support to...
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2021-05-29
Luke Kenneth Casso...
comments
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2021-05-29
Luke Kenneth Casso...
add unit-strided LD/ST ISACaller SVP64 unit test
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