add a quick usage demo to poly1305.py, to serve later as a check
[openpower-isa.git] / src / openpower / decoder / isa /
2023-12-22 Luke Kenneth Casso... add a quick usage demo to poly1305.py, to serve later...
2023-12-22 Luke Kenneth Casso... add implementation of poly1305 pure python
2023-12-22 Luke Kenneth Casso... add code-comments to chacha20 svp64 unit test
2023-12-22 Luke Kenneth Casso... add links copyright and funding notice to svp64 chacha2...
2023-12-22 Jacob Lifshayadd tests for checking if the simulator and assembler...
2023-12-22 Jacob Lifshaylog more register read/writes to LogKind.InstrInOuts
2023-12-22 Jacob Lifshayadd copyright stuff
2023-12-22 Jacob Lifshayadd SVP64 256x256->512-bit multiply
2023-12-22 Andrey MiroshnikovAdding syscall ISACaller test case (not working yet).
2023-12-22 Jacob Lifshayremove grev, leaving unit tests for later use by grevlut
2023-12-22 Jacob Lifshaymake soc test_pipe_caller tests pass again
2023-12-22 Jacob Lifshaymove generated files to .../decoder/isa/generated
2023-12-22 Jacob Lifshayadd set[n]bc[r] -- tests broken
2023-12-22 Jacob Lifshayadd missing test_caller_cr.py
2023-12-22 Jacob Lifshayadd pdepd/pextd
2023-12-22 Jacob Lifshayadd cfuged
2023-12-22 Jacob Lifshayadd cntlzdm/cnttzdm
2023-12-22 Konstantinos Marga... Moved maddsubrs/maddrs/msubrs instructions to separate...
2023-12-22 Jacob Lifshayadd byte reverse instructions from PowerISA v3.1B
2023-12-22 Jacob Lifshayadd fminmax tests with corresponding pseudocode fixes
2023-12-22 Luke Kenneth Casso... leeetle bit excessive on the log of SPRs...
2023-12-22 Jacob Lifshayrename fmv[ft]g*/fcvt[ft]g* to m[tf]fpr*/c[tf]fpr*
2023-12-22 Jacob Lifshayuse the CSV "CR out" column to compute which mode to...
2023-12-22 Jacob Lifshaycache SVP64Instruction.Prefix instance since it's slow...
2023-12-22 Jacob Lifshayremove fcvttgs since it's redundant
2023-12-22 Jacob Lifshaysilence log by default just in fmv/fcvt and utf-8 tests
2023-12-22 Jacob LifshayRevert "disable fmv-fcvt tests entirely"
2023-12-22 Jacob LifshayRevert "far too much memory (58 GB) being used by these...
2023-12-22 Dmitry Selyutininsndb: rename types into core
2023-12-22 Dmitry Selyutininsndb: revert recent renaming
2023-12-22 Luke Kenneth Casso... using names of modules that are identical to commonly...
2023-12-22 Dmitry Selyutinpysvp64asm: integrate into insndb
2023-12-22 Dmitry Selyutinpower_insn: decouple into separate module
2023-06-02 Luke Kenneth Casso... far too much memory (58 GB) being used by these unit...
2023-06-02 Luke Kenneth Casso... disable fmv-fcvt tests entirely
2023-06-02 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=1091
2023-06-02 Luke Kenneth Casso... note on FP Exception about DDFF VLi=0/1
2023-06-02 Jacob LifshayISACaller: generate FP trap
2023-06-02 Luke Kenneth Casso... yet another namespace hack now that @inject is on
2023-06-02 Luke Kenneth Casso... eurrrgh, hack in a namespace dict now that @inject...
2023-06-02 Luke Kenneth Casso... explicitly update FPSCR from list of return results
2023-06-02 Luke Kenneth Casso... code-comment spelling
2023-06-02 Jacob Lifshaycompute CR1 for non-compare fp Rc=1 instructions
2023-06-02 Jacob Lifshayparallelize fmv/fcvt unit tests
2023-06-02 Jacob Lifshayfix CR0 output for fmvtg*/fcvttg*
2023-06-02 Luke Kenneth Casso... replace self.insnlog.append with self.trace function
2023-06-02 Luke Kenneth Casso... got linked-list-pointer-chasing working
2023-06-02 Luke Kenneth Casso... have to now add LD/ST-update instructions to list of...
2023-06-02 Luke Kenneth Casso... attempting to get LD/ST-Update SVP64 EXTRA3 working...
2023-06-02 Luke Kenneth Casso... check expected CR fields in Data-Dependent Fail-First
2023-06-02 Jacob Lifshayadd support for *_flag global variables needed by bfp_...
2023-06-02 Luke Kenneth Casso... corrections to dd-ffirst tests when VLi=0, the write...
2023-06-02 Luke Kenneth Casso... add very very very basic write-out of instruction log
2023-06-02 Jacob Lifshaychange FPSCR to a required parameter of ISACallerHelper
2023-06-02 Jacob LifshayRevert "remove now-unnecessary SO global, since XER...
2023-06-02 Jacob Lifshayadd self.FPSCR
2023-06-02 Jacob Lifshayremove now-unnecessary SO global, since XER[SO] syntax...
2023-06-02 Jacob Lifshayadd support for accessing XER using XER.SO syntax ...
2023-06-02 Luke Kenneth Casso... add ld/st data-dependent fail-first /vli (inclusive)
2023-06-02 Luke Kenneth Casso... fix data-dependent fail-first on load
2023-06-02 Luke Kenneth Casso... extend previous hard-coded magic constant (256) used...
2023-06-02 Luke Kenneth Casso... comment TODO on Load-Fault in strncpy example
2023-06-02 Luke Kenneth Casso... add FPSCR to ISACaller
2023-06-02 Jacob Lifshayadd initial fmv/fcvt tests, though they're broken due...
2023-06-02 Jacob Lifshayadd check that generated .py files are in .gitignore
2023-06-02 Konstantinos Marga... merge maddrs/msubrs, unit tests changed accordingly
2023-06-02 Konstantinos Marga... Add 2 more instructions to help with 2-coeff butterfly
2023-06-02 Konstantinos Marga... WIP: maddsubrs initial approach
2023-06-02 Jacob Lifshayadd fcvt/fmv -- no tests yet
2023-06-02 Jacob Lifshayfix non-zero assembly operands being zero
2023-06-02 Luke Kenneth Casso... reduce number of operands to ffmadds as well
2023-06-02 Jacob Lifshayprefix-sum remap works!
2023-06-02 Jacob Lifshaychange order to tuple in remap preduce tests/demos...
2023-06-02 Luke Kenneth Casso... reduce fdmadds down to only 3 operands, RT-overwrite...
2023-06-02 Luke Kenneth Casso... link in new parallel-prefix REMAP schedule
2023-06-02 Jacob Lifshayadd scan/prefix-sum support to copy of parallel-reduce...
2023-06-02 Jacob Lifshayformat remap_preduce_yield.py
2023-06-02 Luke Kenneth Casso... check RC1, add data-dependent fail-first LD/ST test
2023-06-02 Jacob Lifshayreplace min/max[su][.] with minmax[.]
2023-06-02 Jacob Lifshayadd shaddw
2023-06-02 Luke Kenneth Casso... add power_decode_svp64_rm.py capability for new LD...
2023-06-02 Luke Kenneth Casso... comment about massive unnecessary code-duplication...
2023-06-02 Luke Kenneth Casso... fix setvl unit test which happened to use deprecated
2023-06-02 Jacob Lifshayfix add-like CA/OV outputs
2023-06-02 Jacob Lifshayadd addex to simulator
2023-06-02 Jacob Lifshayfix typo when getting pseudo-code output variables
2023-06-02 Luke Kenneth Casso... remove DCT/iDCT redundant modes which require less...
2023-06-02 Luke Kenneth Casso... updated simplev setvl specification pseudocode: MAJOR...
2023-06-02 Luke Kenneth Casso... whitespace
2023-06-02 Konstantinos Marga... Pass object code filename instead of actual data
2023-06-02 Luke Kenneth Casso... set MAXVL=VL=32 first, then set vertical-first separately
2023-06-02 Konstantinos Marga... used same input data as the actual C test
2023-06-02 Luke Kenneth Casso... change target registers in test_caller_svp64_chacha20...
2023-06-02 Luke Kenneth Casso... whoops use same temp reg for ctr
2023-06-02 Luke Kenneth Casso... parameterise svstep RT (set to 16 in chacha20 test)
2023-06-02 Luke Kenneth Casso... parameterising VL and SHAPE0-2 in chacha20 test
2023-06-02 Luke Kenneth Casso... parameterise the target block in chacha20 test,
2023-06-02 Luke Kenneth Casso... add print-out for chacha20 schedule
2023-06-02 Dmitry Selyutinpower_enums: clean code
2023-06-02 Dmitry Selyutinpower_insn: sort opcodes by sections
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