test_caller_bcd: fix and refactor addg6s test loop
[openpower-isa.git] / src / openpower / decoder / isa /
2021-07-19 Luke Kenneth Casso... update comments and license
2021-07-19 Luke Kenneth Casso... remove unneeded code
2021-07-19 Luke Kenneth Casso... no need for len(j) > 1 test, half of 1 is zero which...
2021-07-19 Luke Kenneth Casso... remove unneeded code
2021-07-19 Luke Kenneth Casso... swap the indices rather than the data in DCT top half...
2021-07-19 Luke Kenneth Casso... remove copy, use in-place with post-inner-loop swap
2021-07-19 Luke Kenneth Casso... add experimental order-reversing code (commented out...
2021-07-19 Luke Kenneth Casso... code comments
2021-07-19 Luke Kenneth Casso... whitespace cleanup
2021-07-19 Luke Kenneth Casso... move bit-reversing to before MULs in DCT
2021-07-19 Luke Kenneth Casso... reverse bit-order of in-place outer DCT butterfly
2021-07-19 Luke Kenneth Casso... finallygot the DCT outer butterfly correct
2021-07-18 Luke Kenneth Casso... got cos intermediate working on iterative dct
2021-07-18 Luke Kenneth Casso... experimenting to create iterative version of dct
2021-07-18 Luke Kenneth Casso... use lists rather than list incomprehension
2021-07-17 Luke Kenneth Casso... print out some debug statements in fastdctlee
2021-07-17 Luke Kenneth Casso... whitespace
2021-07-17 Luke Kenneth Casso... add naive dct, remove fft variant
2021-07-17 Luke Kenneth Casso... add nayuki dct
2021-07-17 Luke Kenneth Casso... working RADIX-2 FFT with bit-reversed LD/ST
2021-07-17 Luke Kenneth Casso... add FP LOAD bit-reversed operations to ISACaller simulator
2021-07-16 Luke Kenneth Casso... add fsins and fcoss to simulator
2021-07-16 Luke Kenneth Casso... add nayuki project reference code
2021-07-15 Luke Kenneth Casso... use coincidence of svremap "persistence" to remove...
2021-07-15 Luke Kenneth Casso... enable use of svremap "persist" mode, remove 4 instruct...
2021-07-15 Luke Kenneth Casso... stop using MSR vfirst bit, move to SVSTATE bit 63 instead
2021-07-15 Luke Kenneth Casso... add extra "persistence" bit to svremap instruction
2021-07-15 Luke Kenneth Casso... big intrusive update: merge SVREMAP with SVSTATE, remov...
2021-07-14 Luke Kenneth Casso... use fmadds and fmsubs in complex fft example
2021-07-14 Luke Kenneth Casso... update SVSTATE to 64 bit length
2021-07-14 Luke Kenneth Casso... subtract one from SVi field for setvl assembler
2021-07-13 Luke Kenneth Casso... change order of log printout for "writing gpr NN"
2021-07-12 Luke Kenneth Casso... successful complex FFT butterfly, in-place, using Verti...
2021-07-12 Luke Kenneth Casso... add a Discrete FFT butterfly unit test as an intermedia...
2021-07-11 Luke Kenneth Casso... minor reordering of setvl and svshape: svshape is now...
2021-07-11 Luke Kenneth Casso... add svremap instruction into ISACaller
2021-07-11 Luke Kenneth Casso... update svremap instruction to correctly store immediate...
2021-07-11 Luke Kenneth Casso... add SVREMAP SPR to ISACaller and parser
2021-07-11 Luke Kenneth Casso... add SVREMAP SPR
2021-07-11 Luke Kenneth Casso... rename SVP64REMAP to SVP64SHAPE
2021-07-11 Luke Kenneth Casso... rename svremap to svshape
2021-07-10 Luke Kenneth Casso... add scalar ffadds unit test
2021-07-10 Luke Kenneth Casso... in scalar case do not increment RB for FFT mode
2021-07-10 Luke Kenneth Casso... add sv.ffadds unit test, inversion of subtract needed...
2021-07-10 Luke Kenneth Casso... more generic allow fft mode 2nd output detection. ...
2021-07-10 Luke Kenneth Casso... add (disabled) FFT complex unit test under development
2021-07-09 Luke Kenneth Casso... update comments
2021-07-09 Luke Kenneth Casso... add svstep variant of fpmadds fft test
2021-07-09 Luke Kenneth Casso... add "odd" SVP64 unit tests which alter SVSTATE
2021-07-09 Luke Kenneth Casso... comments in unit test
2021-07-09 Luke Kenneth Casso... add Vertical-First explicit branch-loop using svstep...
2021-07-08 Luke Kenneth Casso... end SVP64 "Vertical First" mode on rollover when end...
2021-07-08 Luke Kenneth Casso... add CR0 setting and unit test on svstep
2021-07-08 Luke Kenneth Casso... test MSR.SVF bit set after setvl Vertical-First mode set
2021-07-08 Luke Kenneth Casso... whoops must not reset last_op_svstate except when out...
2021-07-08 Luke Kenneth Casso... testing new setvl "svstep" mode
2021-07-08 Luke Kenneth Casso... whoops sv.lfs registers must be even numbers (match...
2021-07-08 Luke Kenneth Casso... add ability to explicitly increment SVSTATE srcstep...
2021-07-08 Luke Kenneth Casso... add in extra "vertical" mode into SVP64 setvl
2021-07-07 Luke Kenneth Casso... clean up imports and unit test name
2021-07-07 Luke Kenneth Casso... ffmuls test, had to add to b not a in expected results
2021-07-07 Luke Kenneth Casso... get butterfly RADIX2 SVP64 example working, breaks...
2021-07-07 Luke Kenneth Casso... add in DFT test from Project Nayuki to verify results...
2021-07-06 Luke Kenneth Casso... change coefficients in FFT REMAP example so as not...
2021-07-06 Luke Kenneth Casso... when REMAP shape is zero, skip it in ISACaller.
2021-07-06 Luke Kenneth Casso... add FFT REMAP butterfly unit test
2021-07-06 Luke Kenneth Casso... add FFT SHAPE pseudocode in svremap, and a schedule...
2021-07-06 Luke Kenneth Casso... add FFT butterfly iteration to SVSHAPE REMAP class...
2021-07-05 Luke Kenneth Casso... add 2nd matrix multiply unit test with SV REMAP
2021-07-05 Luke Kenneth Casso... fix ISACaller FFT-enable detection, fixes sv.fmadds...
2021-07-05 Luke Kenneth Casso... fix svremap field offsets
2021-07-05 Luke Kenneth Casso... whoops, REMAP inverted
2021-07-05 Luke Kenneth Casso... debug of SVP64 REMAP
2021-07-05 Luke Kenneth Casso... debugging SVSHAPE for REMAP
2021-07-05 Luke Kenneth Casso... add in use of SVSHAPE in ISACaller. untested (no damage...
2021-07-05 Luke Kenneth Casso... add last_op_svshape flag to ISACaller
2021-07-05 Luke Kenneth Casso... add svremap manual instruction (Primary Opcode 22,...
2021-07-05 Luke Kenneth Casso... add SVSHAPE class, starting to add to ISACaller
2021-06-29 Luke Kenneth Casso... re-enable accidentally-disabled sv ld/st tests
2021-06-28 Luke Kenneth Casso... add extra offset for FRB, for FFT Cooley-Tukey twin...
2021-06-27 Luke Kenneth Casso... add new SVP64 FFT twin multiply-and-accumulate unit...
2021-06-27 Luke Kenneth Casso... add new (experimental) ffmadds and ffmsubs, for FFT...
2021-06-27 Luke Kenneth Casso... override logic for getting FRS in SVP64 FFT mode
2021-06-26 Luke Kenneth Casso... add LD bit-reversed unit test
2021-06-26 Luke Kenneth Casso... move D const update to after picking up main input...
2021-06-24 Luke Kenneth Casso... whoops fix rounding error in mapreduce unit test
2021-06-23 Luke Kenneth Casso... add ASCII art example to int predicated SVP64
2021-06-23 Luke Kenneth Casso... add VL and srcstep to ISACaller namespace
2021-06-23 Luke Kenneth Casso... better ways to do sign-inversion (without multiply...
2021-06-19 Luke Kenneth Casso... increase number of registers to 128 in pypowersim
2021-06-19 Luke Kenneth Casso... set regfile in ISACaller equal to length of initial...
2021-06-19 Luke Kenneth Casso... add mapreduce "reverse gear" unit tests
2021-06-19 Luke Kenneth Casso... add mapreduce "reverse gear" to PowerDecoder2. gets...
2021-06-15 Luke Kenneth Casso... fix sv_analysis.py for 3R-1W-CRo case, add fmadds/fmsub...
2021-06-15 Luke Kenneth Casso... add fmadds and fmsubs to Power ISA pseudo-code, add...
2021-06-15 Luke Kenneth Casso... add comments into mapreduce example
2021-06-09 Luke Kenneth Casso... add some more comments in the mapreduce svp64 examples...
2021-06-09 Luke Kenneth Casso... add sv.fmuls/mr - mapreduce - FP multiply-single test
2021-06-09 Luke Kenneth Casso... add first scalar mapreduce SVP64 example
2021-06-08 Luke Kenneth Casso... whoops, carry-over during rounding picks MSB not LSB
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